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Fix typecode generation for tcg helpers

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Fix single stepping into interrupt handlers
 Fix out-of-range offsets for stores in TCI
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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220228' into staging

Fix typecode generation for tcg helpers
Fix single stepping into interrupt handlers
Fix out-of-range offsets for stores in TCI

# gpg: Signature made Mon 28 Feb 2022 18:07:13 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20220228:
  tcg/tci: Use tcg_out_ldst in tcg_out_st
  accel/tcg/cpu-exec: Fix precise single-stepping after interrupt
  tcg: Remove dh_alias indirection for dh_typecode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-01 15:55:31 +00:00
commit 09591fcf6e
7 changed files with 27 additions and 14 deletions
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8
accel/tcg/cpu-exec.c
View File

@ -799,8 +799,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
* raised when single-stepping so that GDB doesn't miss the
* next instruction.
*/
cpu->exception_index =
(cpu->singlestep_enabled ? EXCP_DEBUG : -1);
if (unlikely(cpu->singlestep_enabled)) {
cpu->exception_index = EXCP_DEBUG;
qemu_mutex_unlock_iothread();
return true;
}
cpu->exception_index = -1;
*last_tb = NULL;
}
/* The target hook may have updated the 'cpu->interrupt_request';

19
include/exec/helper-head.h
View File

@ -53,13 +53,16 @@
# ifdef TARGET_LONG_BITS
# if TARGET_LONG_BITS == 32
# define dh_alias_tl i32
# define dh_typecode_tl dh_typecode_i32
# else
# define dh_alias_tl i64
# define dh_typecode_tl dh_typecode_i64
# endif
# endif
# define dh_alias_env ptr
# define dh_ctype_tl target_ulong
# define dh_alias_env ptr
# define dh_ctype_env CPUArchState *
# define dh_typecode_env dh_typecode_ptr
#endif
/* We can't use glue() here because it falls foul of C preprocessor
@ -92,18 +95,16 @@
#define dh_typecode_i64 4
#define dh_typecode_s64 5
#define dh_typecode_ptr 6
#define dh_typecode(t) glue(dh_typecode_, dh_alias(t))
#define dh_typecode_int dh_typecode_s32
#define dh_typecode_f16 dh_typecode_i32
#define dh_typecode_f32 dh_typecode_i32
#define dh_typecode_f64 dh_typecode_i64
#define dh_typecode_cptr dh_typecode_ptr
#define dh_typecode(t) dh_typecode_##t
#define dh_callflag_i32 0
#define dh_callflag_s32 0
#define dh_callflag_int 0
#define dh_callflag_i64 0
#define dh_callflag_s64 0
#define dh_callflag_f16 0
#define dh_callflag_f32 0
#define dh_callflag_f64 0
#define dh_callflag_ptr 0
#define dh_callflag_cptr dh_callflag_ptr
#define dh_callflag_void 0
#define dh_callflag_noreturn TCG_CALL_NO_RETURN
#define dh_callflag(t) glue(dh_callflag_, dh_alias(t))

2
target/hppa/helper.h
View File

@ -1,7 +1,9 @@
#if TARGET_REGISTER_BITS == 64
# define dh_alias_tr i64
# define dh_typecode_tr dh_typecode_i64
#else
# define dh_alias_tr i32
# define dh_typecode_tr dh_typecode_i32
#endif
#define dh_ctype_tr target_ureg

3
target/i386/ops_sse_header.h
View File

@ -30,6 +30,9 @@
#define dh_ctype_Reg Reg *
#define dh_ctype_ZMMReg ZMMReg *
#define dh_ctype_MMXReg MMXReg *
#define dh_typecode_Reg dh_typecode_ptr
#define dh_typecode_ZMMReg dh_typecode_ptr
#define dh_typecode_MMXReg dh_typecode_ptr
DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)

1
target/m68k/helper.h
View File

@ -17,6 +17,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
#define dh_alias_fp ptr
#define dh_ctype_fp FPReg *
#define dh_typecode_fp dh_typecode_ptr
DEF_HELPER_3(exts32, void, env, fp, s32)
DEF_HELPER_3(extf32, void, env, fp, f32)

3
target/ppc/helper.h
View File

@ -127,9 +127,11 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_alias_avr ptr
#define dh_ctype_avr ppc_avr_t *
#define dh_typecode_avr dh_typecode_ptr
#define dh_alias_vsr ptr
#define dh_ctype_vsr ppc_vsr_t *
#define dh_typecode_vsr dh_typecode_ptr
DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
@ -708,6 +710,7 @@ DEF_HELPER_3(store_dbatu, void, env, i32, tl)
#define dh_alias_fprp ptr
#define dh_ctype_fprp ppc_fprp_t *
#define dh_typecode_fprp dh_typecode_ptr
DEF_HELPER_4(DADD, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DADDQ, void, env, fprp, fprp, fprp)

5
tcg/tci/tcg-target.c.inc
View File

@ -790,14 +790,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
intptr_t offset)
{
stack_bounds_check(base, offset);
switch (type) {
case TCG_TYPE_I32:
tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
tcg_out_ldst(s, INDEX_op_st_i32, val, base, offset);
break;
#if TCG_TARGET_REG_BITS == 64
case TCG_TYPE_I64:
tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
tcg_out_ldst(s, INDEX_op_st_i64, val, base, offset);
break;
#endif
default: