mirror of https://gitlab.com/qemu-project/qemu
target/arm: Add BT and BTYPE to tb->flags
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3052,6 +3052,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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FIELD(TBFLAG_A64, BT, 9, 1)
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FIELD(TBFLAG_A64, BTYPE, 10, 2)
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static inline bool bswap_code(bool sctlr_b)
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static inline bool bswap_code(bool sctlr_b)
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{
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{
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@ -13735,6 +13735,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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if (is_a64(env)) {
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if (is_a64(env)) {
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint64_t sctlr;
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*pc = env->pc;
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*pc = env->pc;
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
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@ -13779,6 +13780,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
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flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
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}
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}
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if (current_el == 0) {
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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sctlr = env->cp15.sctlr_el[1];
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} else {
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sctlr = env->cp15.sctlr_el[current_el];
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}
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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/*
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/*
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* In order to save space in flags, we record only whether
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* In order to save space in flags, we record only whether
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@ -13786,17 +13793,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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* a nop, or "active" when some action must be performed.
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* a nop, or "active" when some action must be performed.
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* The decision of which action to take is left to a helper.
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* The decision of which action to take is left to a helper.
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*/
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*/
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uint64_t sctlr;
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if (current_el == 0) {
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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sctlr = env->cp15.sctlr_el[1];
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} else {
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sctlr = env->cp15.sctlr_el[current_el];
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}
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
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flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
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}
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}
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}
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}
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if (cpu_isar_feature(aa64_bti, cpu)) {
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/* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
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if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
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}
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flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
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}
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} else {
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} else {
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*pc = env->regs[15];
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*pc = env->regs[15];
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flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
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flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
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@ -13840,6 +13840,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
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dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
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dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
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dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
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dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
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dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
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dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
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dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
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dc->vec_len = 0;
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dc->vec_len = 0;
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dc->vec_stride = 0;
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dc->vec_stride = 0;
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dc->cp_regs = arm_cpu->cp_regs;
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dc->cp_regs = arm_cpu->cp_regs;
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@ -69,6 +69,10 @@ typedef struct DisasContext {
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bool ss_same_el;
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bool ss_same_el;
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/* True if v8.3-PAuth is active. */
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/* True if v8.3-PAuth is active. */
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bool pauth_active;
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bool pauth_active;
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/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
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bool bt;
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/* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */
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uint8_t btype;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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int c15_cpar;
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/* TCG op of the current insn_start. */
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/* TCG op of the current insn_start. */
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