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target/ppc: optimize p7 exception handling routines

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Like p8 and p9, simplifying p7 exception handling rotuines to avoid
un-necessary multiple indirect accesses to env->pending_interrupts and
env->spr[SPR_LPCR].

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Harsh Prateek Bora 2024-10-10 11:17:37 +05:30 committed by Nicholas Piggin
parent 37e62398ab
commit 085cc36496
1 changed files with 25 additions and 21 deletions
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46
target/ppc/excp_helper.c
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@ -1683,51 +1683,54 @@ void ppc_cpu_do_interrupt(CPUState *cs)
PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \ PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \
PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB) PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB)
static int p7_interrupt_powersave(CPUPPCState *env) static int p7_interrupt_powersave(uint32_t pending_interrupts,
target_ulong lpcr)
{ {
if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && if ((pending_interrupts & PPC_INTERRUPT_EXT) &&
(env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { (lpcr & LPCR_P7_PECE0)) {
return PPC_INTERRUPT_EXT; return PPC_INTERRUPT_EXT;
} }
if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && if ((pending_interrupts & PPC_INTERRUPT_DECR) &&
(env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { (lpcr & LPCR_P7_PECE1)) {
return PPC_INTERRUPT_DECR; return PPC_INTERRUPT_DECR;
} }
if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && if ((pending_interrupts & PPC_INTERRUPT_MCK) &&
(env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { (lpcr & LPCR_P7_PECE2)) {
return PPC_INTERRUPT_MCK; return PPC_INTERRUPT_MCK;
} }
if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && if ((pending_interrupts & PPC_INTERRUPT_HMI) &&
(env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { (lpcr & LPCR_P7_PECE2)) {
return PPC_INTERRUPT_HMI; return PPC_INTERRUPT_HMI;
} }
if (env->pending_interrupts & PPC_INTERRUPT_RESET) { if (pending_interrupts & PPC_INTERRUPT_RESET) {
return PPC_INTERRUPT_RESET; return PPC_INTERRUPT_RESET;
} }
return 0; return 0;
} }
static int p7_next_unmasked_interrupt(CPUPPCState *env) static int p7_next_unmasked_interrupt(CPUPPCState *env,
uint32_t pending_interrupts,
target_ulong lpcr)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
/* Ignore MSR[EE] when coming out of some power management states */ /* Ignore MSR[EE] when coming out of some power management states */
bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
assert((env->pending_interrupts & P7_UNUSED_INTERRUPTS) == 0); assert((pending_interrupts & P7_UNUSED_INTERRUPTS) == 0);
if (cs->halted) { if (cs->halted) {
/* LPCR[PECE] controls which interrupts can exit power-saving mode */ /* LPCR[PECE] controls which interrupts can exit power-saving mode */
return p7_interrupt_powersave(env); return p7_interrupt_powersave(pending_interrupts, lpcr);
} }
/* Machine check exception */ /* Machine check exception */
if (env->pending_interrupts & PPC_INTERRUPT_MCK) { if (pending_interrupts & PPC_INTERRUPT_MCK) {
return PPC_INTERRUPT_MCK; return PPC_INTERRUPT_MCK;
} }
/* Hypervisor decrementer exception */ /* Hypervisor decrementer exception */
if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { if (pending_interrupts & PPC_INTERRUPT_HDECR) {
/* LPCR will be clear when not supported so this will work */ /* LPCR will be clear when not supported so this will work */
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
@ -1737,9 +1740,9 @@ static int p7_next_unmasked_interrupt(CPUPPCState *env)
} }
/* External interrupt can ignore MSR:EE under some circumstances */ /* External interrupt can ignore MSR:EE under some circumstances */
if (env->pending_interrupts & PPC_INTERRUPT_EXT) { if (pending_interrupts & PPC_INTERRUPT_EXT) {
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool lpes0 = !!(lpcr & LPCR_LPES0);
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); bool heic = !!(lpcr & LPCR_HEIC);
/* HEIC blocks delivery to the hypervisor */ /* HEIC blocks delivery to the hypervisor */
if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) &&
!FIELD_EX64(env->msr, MSR, PR))) || !FIELD_EX64(env->msr, MSR, PR))) ||
@ -1749,10 +1752,10 @@ static int p7_next_unmasked_interrupt(CPUPPCState *env)
} }
if (msr_ee != 0) { if (msr_ee != 0) {
/* Decrementer exception */ /* Decrementer exception */
if (env->pending_interrupts & PPC_INTERRUPT_DECR) { if (pending_interrupts & PPC_INTERRUPT_DECR) {
return PPC_INTERRUPT_DECR; return PPC_INTERRUPT_DECR;
} }
if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { if (pending_interrupts & PPC_INTERRUPT_PERFM) {
return PPC_INTERRUPT_PERFM; return PPC_INTERRUPT_PERFM;
} }
} }
@ -2022,7 +2025,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
#ifdef TARGET_PPC64 #ifdef TARGET_PPC64
switch (env->excp_model) { switch (env->excp_model) {
case POWERPC_EXCP_POWER7: case POWERPC_EXCP_POWER7:
return p7_next_unmasked_interrupt(env); return p7_next_unmasked_interrupt(env, env->pending_interrupts,
env->spr[SPR_LPCR]);
case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER8:
return p8_next_unmasked_interrupt(env, env->pending_interrupts, return p8_next_unmasked_interrupt(env, env->pending_interrupts,
env->spr[SPR_LPCR]); env->spr[SPR_LPCR]);