tcg/i386: use movbe instruction in qemu_ldst routines
The movbe instruction has been added on some Intel Atom CPUs and on recent Intel Haswell CPUs. It allows to load/store a value and at the same time bswap it. This patch detects the avaibility of this instruction and when available use it in the qemu load/store routines in replacement of load/store + bswap. Note that for 16-bit unsigned loads, movbe + movzw is basically the same as movzw + bswap, so the patch doesn't touch this case. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [RTH: Reduced the number of conditionals using "movop".] Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -99,18 +99,31 @@ static const int tcg_target_call_oarg_regs[] = {
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# define TCG_REG_L1 TCG_REG_EDX
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#endif
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/* The host compiler should supply <cpuid.h> to enable runtime features
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detection, as we're not going to go so far as our own inline assembly.
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If not available, default values will be assumed. */
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#if defined(CONFIG_CPUID_H)
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#include <cpuid.h>
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#endif
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/* For 32-bit, we are going to attempt to determine at runtime whether cmov
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is available. However, the host compiler must supply <cpuid.h>, as we're
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not going to go so far as our own inline assembly. */
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is available. */
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#if TCG_TARGET_REG_BITS == 64
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# define have_cmov 1
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#elif defined(CONFIG_CPUID_H)
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#include <cpuid.h>
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static bool have_cmov;
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#else
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# define have_cmov 0
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#endif
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/* If bit_MOVBE is defined in cpuid.h (added in GCC version 4.6), we are
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going to attempt to determine at runtime whether movbe is available. */
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#if defined(CONFIG_CPUID_H) && defined(bit_MOVBE)
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static bool have_movbe;
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#else
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# define have_movbe 0
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#endif
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type,
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@ -280,6 +293,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define OPC_MOVB_EvIz (0xc6)
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#define OPC_MOVL_EvIz (0xc7)
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#define OPC_MOVL_Iv (0xb8)
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#define OPC_MOVBE_GyMy (0xf0 | P_EXT38)
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#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
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#define OPC_MOVSBL (0xbe | P_EXT)
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#define OPC_MOVSWL (0xbf | P_EXT)
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#define OPC_MOVSLQ (0x63 | P_REXW)
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@ -1344,7 +1359,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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const TCGMemOp bswap = memop & MO_BSWAP;
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const TCGMemOp real_bswap = memop & MO_BSWAP;
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TCGMemOp bswap = real_bswap;
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int movop = OPC_MOVL_GvEv;
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if (have_movbe && real_bswap) {
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bswap = 0;
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movop = OPC_MOVBE_GyMy;
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}
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switch (memop & MO_SSIZE) {
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case MO_UB:
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@ -1355,14 +1377,19 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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break;
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case MO_UW:
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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if (bswap) {
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if (real_bswap) {
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tcg_out_rolw_8(s, datalo);
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}
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break;
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case MO_SW:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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tcg_out_rolw_8(s, datalo);
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if (real_bswap) {
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if (have_movbe) {
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tcg_out_modrm_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
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datalo, base, ofs);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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tcg_out_rolw_8(s, datalo);
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}
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tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW + seg,
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@ -1370,16 +1397,18 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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}
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break;
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case MO_UL:
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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}
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break;
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#if TCG_TARGET_REG_BITS == 64
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case MO_SL:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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tcg_out_bswap32(s, datalo);
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if (real_bswap) {
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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}
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tcg_out_ext32s(s, datalo, datalo);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVSLQ + seg, datalo, base, ofs);
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@ -1388,27 +1417,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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#endif
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case MO_Q:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + P_REXW + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap64(s, datalo);
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}
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} else {
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if (bswap) {
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if (real_bswap) {
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int t = datalo;
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datalo = datahi;
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datahi = t;
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}
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if (base != datalo) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datahi, base, ofs + 4);
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs + 4);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datahi, base, ofs + 4);
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs + 4);
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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}
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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@ -1484,13 +1508,19 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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const TCGMemOp bswap = memop & MO_BSWAP;
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/* ??? Ideally we wouldn't need a scratch register. For user-only,
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we could perform the bswap twice to restore the original value
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instead of moving to the scratch. But as it is, the L constraint
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means that TCG_REG_L0 is definitely free here. */
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const TCGReg scratch = TCG_REG_L0;
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const TCGMemOp real_bswap = memop & MO_BSWAP;
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TCGMemOp bswap = real_bswap;
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int movop = OPC_MOVL_EvGv;
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if (have_movbe && real_bswap) {
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bswap = 0;
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movop = OPC_MOVBE_MyGy;
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}
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switch (memop & MO_SIZE) {
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case MO_8:
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@ -1509,8 +1539,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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tcg_out_rolw_8(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16 + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs);
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break;
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case MO_32:
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if (bswap) {
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@ -1518,7 +1547,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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tcg_out_bswap32(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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break;
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case MO_64:
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if (TCG_TARGET_REG_BITS == 64) {
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@ -1527,8 +1556,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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tcg_out_bswap64(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_REXW + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, ofs);
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} else if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
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tcg_out_bswap32(s, scratch);
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@ -1537,8 +1565,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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tcg_out_bswap32(s, scratch);
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs+4);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datahi, base, ofs+4);
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if (real_bswap) {
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int t = datalo;
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datalo = datahi;
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datahi = t;
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}
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tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs+4);
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}
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break;
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default:
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@ -2165,13 +2198,23 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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static void tcg_target_init(TCGContext *s)
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{
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/* For 32-bit, 99% certainty that we're running on hardware that supports
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cmov, but we still need to check. In case cmov is not available, we'll
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use a small forward branch. */
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#ifndef have_cmov
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#if !(defined(have_cmov) && defined(have_movbe))
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{
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unsigned a, b, c, d;
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have_cmov = (__get_cpuid(1, &a, &b, &c, &d) && (d & bit_CMOV));
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int ret = __get_cpuid(1, &a, &b, &c, &d);
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# ifndef have_cmov
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/* For 32-bit, 99% certainty that we're running on hardware that
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supports cmov, but we still need to check. In case cmov is not
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available, we'll use a small forward branch. */
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have_cmov = ret && (d & bit_CMOV);
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# endif
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# ifndef have_movbe
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/* MOVBE is only available on Intel Atom and Haswell CPUs, so we
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need to probe for it. */
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have_movbe = ret && (c & bit_MOVBE);
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# endif
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}
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#endif
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