target-arm: Abstract out load/store from a vaddr in AArch32
AArch32 code (ie traditional 32 bit world) expects to be able to pass a vaddr in a TCGv_i32. However when QEMU is compiled with TARGET_LONG_BITS=32 the TCG load/store functions take a TCGv_i64. Abstract out load/store with a 32 bit vaddr so we have a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org
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@ -843,6 +843,90 @@ static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
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}
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}
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}
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}
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/* Abstractions of "generate code to do a guest load/store for
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* AArch32", where a vaddr is always 32 bits (and is zero
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* extended if we're a 64 bit core) and data is also
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* 32 bits unless specifically doing a 64 bit access.
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* These functions work like tcg_gen_qemu_{ld,st}* except
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* that their arguments are TCGv_i32 rather than TCGv.
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*/
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#if TARGET_LONG_BITS == 32
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#define DO_GEN_LD(OP) \
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static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
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{ \
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tcg_gen_qemu_##OP(val, addr, index); \
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}
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#define DO_GEN_ST(OP) \
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static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
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{ \
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tcg_gen_qemu_##OP(val, addr, index); \
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}
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static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
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{
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tcg_gen_qemu_ld64(val, addr, index);
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}
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static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
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{
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tcg_gen_qemu_st64(val, addr, index);
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}
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#else
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#define DO_GEN_LD(OP) \
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static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
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{ \
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TCGv addr64 = tcg_temp_new(); \
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TCGv val64 = tcg_temp_new(); \
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tcg_gen_extu_i32_i64(addr64, addr); \
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tcg_gen_qemu_##OP(val64, addr64, index); \
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tcg_temp_free(addr64); \
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tcg_gen_trunc_i64_i32(val, val64); \
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tcg_temp_free(val64); \
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}
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#define DO_GEN_ST(OP) \
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static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
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{ \
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TCGv addr64 = tcg_temp_new(); \
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TCGv val64 = tcg_temp_new(); \
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tcg_gen_extu_i32_i64(addr64, addr); \
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tcg_gen_extu_i32_i64(val64, val); \
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tcg_gen_qemu_##OP(val64, addr64, index); \
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tcg_temp_free(addr64); \
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tcg_temp_free(val64); \
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}
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static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
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{
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TCGv addr64 = tcg_temp_new();
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tcg_gen_extu_i32_i64(addr64, addr);
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tcg_gen_qemu_ld64(val, addr64, index);
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tcg_temp_free(addr64);
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}
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static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
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{
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TCGv addr64 = tcg_temp_new();
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tcg_gen_extu_i32_i64(addr64, addr);
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tcg_gen_qemu_st64(val, addr64, index);
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tcg_temp_free(addr64);
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}
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#endif
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DO_GEN_LD(ld8s)
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DO_GEN_LD(ld8u)
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DO_GEN_LD(ld16s)
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DO_GEN_LD(ld16u)
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DO_GEN_LD(ld32u)
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DO_GEN_ST(st8)
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DO_GEN_ST(st16)
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DO_GEN_ST(st32)
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static inline void gen_set_pc_im(uint32_t val)
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static inline void gen_set_pc_im(uint32_t val)
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{
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{
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tcg_gen_movi_i32(cpu_R[15], val);
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tcg_gen_movi_i32(cpu_R[15], val);
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@ -1072,18 +1156,20 @@ VFP_GEN_FIX(ulto)
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static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
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static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
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{
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{
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if (dp)
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if (dp) {
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tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
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gen_aa32_ld64(cpu_F0d, addr, IS_USER(s));
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else
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} else {
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tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
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gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s));
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}
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}
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}
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static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
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static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
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{
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{
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if (dp)
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if (dp) {
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tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
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gen_aa32_st64(cpu_F0d, addr, IS_USER(s));
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else
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} else {
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tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
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gen_aa32_st32(cpu_F0s, addr, IS_USER(s));
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}
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}
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}
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static inline long
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static inline long
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@ -1420,24 +1506,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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if (insn & ARM_CP_RW_BIT) {
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if (insn & ARM_CP_RW_BIT) {
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if ((insn >> 28) == 0xf) { /* WLDRW wCx */
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if ((insn >> 28) == 0xf) { /* WLDRW wCx */
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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gen_aa32_ld32u(tmp, addr, IS_USER(s));
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iwmmxt_store_creg(wrd, tmp);
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iwmmxt_store_creg(wrd, tmp);
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} else {
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} else {
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i = 1;
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i = 1;
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if (insn & (1 << 8)) {
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if (insn & (1 << 8)) {
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if (insn & (1 << 22)) { /* WLDRD */
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if (insn & (1 << 22)) { /* WLDRD */
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tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
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gen_aa32_ld64(cpu_M0, addr, IS_USER(s));
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i = 0;
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i = 0;
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} else { /* WLDRW wRd */
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} else { /* WLDRW wRd */
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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gen_aa32_ld32u(tmp, addr, IS_USER(s));
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}
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}
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} else {
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} else {
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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if (insn & (1 << 22)) { /* WLDRH */
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if (insn & (1 << 22)) { /* WLDRH */
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tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
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gen_aa32_ld16u(tmp, addr, IS_USER(s));
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} else { /* WLDRB */
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} else { /* WLDRB */
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tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
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gen_aa32_ld8u(tmp, addr, IS_USER(s));
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}
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}
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}
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}
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if (i) {
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if (i) {
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@ -1449,24 +1535,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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} else {
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} else {
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if ((insn >> 28) == 0xf) { /* WSTRW wCx */
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if ((insn >> 28) == 0xf) { /* WSTRW wCx */
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tmp = iwmmxt_load_creg(wrd);
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tmp = iwmmxt_load_creg(wrd);
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tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
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gen_aa32_st32(tmp, addr, IS_USER(s));
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} else {
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} else {
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gen_op_iwmmxt_movq_M0_wRn(wrd);
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gen_op_iwmmxt_movq_M0_wRn(wrd);
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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if (insn & (1 << 8)) {
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if (insn & (1 << 8)) {
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if (insn & (1 << 22)) { /* WSTRD */
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if (insn & (1 << 22)) { /* WSTRD */
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tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
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gen_aa32_st64(cpu_M0, addr, IS_USER(s));
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} else { /* WSTRW wRd */
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} else { /* WSTRW wRd */
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
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gen_aa32_st32(tmp, addr, IS_USER(s));
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}
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}
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} else {
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} else {
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if (insn & (1 << 22)) { /* WSTRH */
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if (insn & (1 << 22)) { /* WSTRH */
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
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gen_aa32_st16(tmp, addr, IS_USER(s));
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} else { /* WSTRB */
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} else { /* WSTRB */
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_trunc_i64_i32(tmp, cpu_M0);
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tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
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gen_aa32_st8(tmp, addr, IS_USER(s));
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}
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}
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}
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}
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}
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}
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@ -2531,15 +2617,15 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGv_i32 tmp = tcg_temp_new_i32();
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switch (size) {
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switch (size) {
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case 0:
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case 0:
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tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
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gen_aa32_ld8u(tmp, addr, IS_USER(s));
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gen_neon_dup_u8(tmp, 0);
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gen_neon_dup_u8(tmp, 0);
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break;
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break;
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case 1:
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case 1:
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tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
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gen_aa32_ld16u(tmp, addr, IS_USER(s));
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gen_neon_dup_low16(tmp);
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gen_neon_dup_low16(tmp);
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break;
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break;
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case 2:
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case 2:
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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gen_aa32_ld32u(tmp, addr, IS_USER(s));
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break;
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break;
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default: /* Avoid compiler warnings. */
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default: /* Avoid compiler warnings. */
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abort();
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abort();
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@ -3817,11 +3903,11 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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if (size == 3) {
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if (size == 3) {
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tmp64 = tcg_temp_new_i64();
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tmp64 = tcg_temp_new_i64();
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if (load) {
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if (load) {
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tcg_gen_qemu_ld64(tmp64, addr, IS_USER(s));
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gen_aa32_ld64(tmp64, addr, IS_USER(s));
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neon_store_reg64(tmp64, rd);
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neon_store_reg64(tmp64, rd);
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} else {
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} else {
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neon_load_reg64(tmp64, rd);
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neon_load_reg64(tmp64, rd);
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tcg_gen_qemu_st64(tmp64, addr, IS_USER(s));
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gen_aa32_st64(tmp64, addr, IS_USER(s));
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}
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}
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tcg_temp_free_i64(tmp64);
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tcg_temp_free_i64(tmp64);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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@ -3830,21 +3916,21 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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if (size == 2) {
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if (size == 2) {
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if (load) {
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if (load) {
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
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gen_aa32_ld32u(tmp, addr, IS_USER(s));
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neon_store_reg(rd, pass, tmp);
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neon_store_reg(rd, pass, tmp);
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} else {
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} else {
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tmp = neon_load_reg(rd, pass);
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tmp = neon_load_reg(rd, pass);
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tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
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gen_aa32_st32(tmp, addr, IS_USER(s));
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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}
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}
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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} else if (size == 1) {
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} else if (size == 1) {
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if (load) {
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if (load) {
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
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gen_aa32_ld16u(tmp, addr, IS_USER(s));
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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tmp2 = tcg_temp_new_i32();
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tmp2 = tcg_temp_new_i32();
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tcg_gen_qemu_ld16u(tmp2, addr, IS_USER(s));
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gen_aa32_ld16u(tmp2, addr, IS_USER(s));
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_shli_i32(tmp2, tmp2, 16);
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tcg_gen_shli_i32(tmp2, tmp2, 16);
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tcg_gen_or_i32(tmp, tmp, tmp2);
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tcg_gen_or_i32(tmp, tmp, tmp2);
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@ -3854,10 +3940,10 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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tmp = neon_load_reg(rd, pass);
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tmp = neon_load_reg(rd, pass);
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tmp2 = tcg_temp_new_i32();
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tmp2 = tcg_temp_new_i32();
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tcg_gen_shri_i32(tmp2, tmp, 16);
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tcg_gen_shri_i32(tmp2, tmp, 16);
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tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
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gen_aa32_st16(tmp, addr, IS_USER(s));
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_qemu_st16(tmp2, addr, IS_USER(s));
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gen_aa32_st16(tmp2, addr, IS_USER(s));
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tcg_temp_free_i32(tmp2);
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tcg_temp_free_i32(tmp2);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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}
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}
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@ -3866,7 +3952,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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TCGV_UNUSED_I32(tmp2);
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TCGV_UNUSED_I32(tmp2);
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for (n = 0; n < 4; n++) {
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for (n = 0; n < 4; n++) {
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tmp = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
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gen_aa32_ld8u(tmp, addr, IS_USER(s));
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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if (n == 0) {
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if (n == 0) {
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tmp2 = tmp;
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tmp2 = tmp;
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@ -3886,7 +3972,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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} else {
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} else {
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tcg_gen_shri_i32(tmp, tmp2, n * 8);
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tcg_gen_shri_i32(tmp, tmp2, n * 8);
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}
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}
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tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
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gen_aa32_st8(tmp, addr, IS_USER(s));
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_addi_i32(addr, addr, stride);
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}
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}
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@ -4010,13 +4096,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default: /* Avoid compiler warnings. */
|
default: /* Avoid compiler warnings. */
|
||||||
abort();
|
abort();
|
||||||
@ -4034,13 +4120,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
|
|||||||
tcg_gen_shri_i32(tmp, tmp, shift);
|
tcg_gen_shri_i32(tmp, tmp, shift);
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
@ -6464,14 +6550,14 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
|
|||||||
|
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
case 3:
|
case 3:
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -6482,7 +6568,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
|
|||||||
TCGv_i32 tmp2 = tcg_temp_new_i32();
|
TCGv_i32 tmp2 = tcg_temp_new_i32();
|
||||||
tcg_gen_addi_i32(tmp2, addr, 4);
|
tcg_gen_addi_i32(tmp2, addr, 4);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
|
gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp2);
|
tcg_temp_free_i32(tmp2);
|
||||||
tcg_gen_mov_i32(cpu_exclusive_high, tmp);
|
tcg_gen_mov_i32(cpu_exclusive_high, tmp);
|
||||||
store_reg(s, rt2, tmp);
|
store_reg(s, rt2, tmp);
|
||||||
@ -6524,14 +6610,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
|
|||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
case 3:
|
case 3:
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -6542,7 +6628,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
|
|||||||
TCGv_i32 tmp2 = tcg_temp_new_i32();
|
TCGv_i32 tmp2 = tcg_temp_new_i32();
|
||||||
tcg_gen_addi_i32(tmp2, addr, 4);
|
tcg_gen_addi_i32(tmp2, addr, 4);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
|
gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp2);
|
tcg_temp_free_i32(tmp2);
|
||||||
tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
|
tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
@ -6550,14 +6636,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
|
|||||||
tmp = load_reg(s, rt);
|
tmp = load_reg(s, rt);
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
case 3:
|
case 3:
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -6566,7 +6652,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
|
|||||||
if (size == 3) {
|
if (size == 3) {
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp = load_reg(s, rt2);
|
tmp = load_reg(s, rt2);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_gen_movi_i32(cpu_R[rd], 0);
|
tcg_gen_movi_i32(cpu_R[rd], 0);
|
||||||
@ -6613,11 +6699,11 @@ static void gen_srs(DisasContext *s,
|
|||||||
}
|
}
|
||||||
tcg_gen_addi_i32(addr, addr, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
tmp = load_reg(s, 14);
|
tmp = load_reg(s, 14);
|
||||||
tcg_gen_qemu_st32(tmp, addr, 0);
|
gen_aa32_st32(tmp, addr, 0);
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tmp = load_cpu_field(spsr);
|
tmp = load_cpu_field(spsr);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tcg_gen_qemu_st32(tmp, addr, 0);
|
gen_aa32_st32(tmp, addr, 0);
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
if (writeback) {
|
if (writeback) {
|
||||||
switch (amode) {
|
switch (amode) {
|
||||||
@ -6763,10 +6849,10 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
tcg_gen_addi_i32(addr, addr, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
/* Load PC into tmp and CPSR into tmp2. */
|
/* Load PC into tmp and CPSR into tmp2. */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, 0);
|
gen_aa32_ld32u(tmp, addr, 0);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp2 = tcg_temp_new_i32();
|
tmp2 = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp2, addr, 0);
|
gen_aa32_ld32u(tmp2, addr, 0);
|
||||||
if (insn & (1 << 21)) {
|
if (insn & (1 << 21)) {
|
||||||
/* Base writeback. */
|
/* Base writeback. */
|
||||||
switch (i) {
|
switch (i) {
|
||||||
@ -7322,13 +7408,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch (op1) {
|
switch (op1) {
|
||||||
case 0: /* lda */
|
case 0: /* lda */
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2: /* ldab */
|
case 2: /* ldab */
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 3: /* ldah */
|
case 3: /* ldah */
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -7339,13 +7425,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
tmp = load_reg(s, rm);
|
tmp = load_reg(s, rm);
|
||||||
switch (op1) {
|
switch (op1) {
|
||||||
case 0: /* stl */
|
case 0: /* stl */
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2: /* stlb */
|
case 2: /* stlb */
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 3: /* stlh */
|
case 3: /* stlh */
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -7400,11 +7486,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
tmp = load_reg(s, rm);
|
tmp = load_reg(s, rm);
|
||||||
tmp2 = tcg_temp_new_i32();
|
tmp2 = tcg_temp_new_i32();
|
||||||
if (insn & (1 << 22)) {
|
if (insn & (1 << 22)) {
|
||||||
tcg_gen_qemu_ld8u(tmp2, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp2, addr, IS_USER(s));
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
} else {
|
} else {
|
||||||
tcg_gen_qemu_ld32u(tmp2, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp2, addr, IS_USER(s));
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
@ -7426,14 +7512,14 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch(sh) {
|
switch(sh) {
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
|
gen_aa32_ld8s(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
case 3:
|
case 3:
|
||||||
tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
|
gen_aa32_ld16s(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
load = 1;
|
load = 1;
|
||||||
@ -7443,21 +7529,21 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
if (sh & 1) {
|
if (sh & 1) {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp = load_reg(s, rd + 1);
|
tmp = load_reg(s, rd + 1);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
load = 0;
|
load = 0;
|
||||||
} else {
|
} else {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
rd++;
|
rd++;
|
||||||
load = 1;
|
load = 1;
|
||||||
}
|
}
|
||||||
@ -7465,7 +7551,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
load = 0;
|
load = 0;
|
||||||
}
|
}
|
||||||
@ -7798,17 +7884,17 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
if (insn & (1 << 22)) {
|
if (insn & (1 << 22)) {
|
||||||
tcg_gen_qemu_ld8u(tmp, tmp2, i);
|
gen_aa32_ld8u(tmp, tmp2, i);
|
||||||
} else {
|
} else {
|
||||||
tcg_gen_qemu_ld32u(tmp, tmp2, i);
|
gen_aa32_ld32u(tmp, tmp2, i);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
if (insn & (1 << 22)) {
|
if (insn & (1 << 22)) {
|
||||||
tcg_gen_qemu_st8(tmp, tmp2, i);
|
gen_aa32_st8(tmp, tmp2, i);
|
||||||
} else {
|
} else {
|
||||||
tcg_gen_qemu_st32(tmp, tmp2, i);
|
gen_aa32_st32(tmp, tmp2, i);
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
@ -7875,7 +7961,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
if (insn & (1 << 20)) {
|
if (insn & (1 << 20)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
if (user) {
|
if (user) {
|
||||||
tmp2 = tcg_const_i32(i);
|
tmp2 = tcg_const_i32(i);
|
||||||
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
|
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
|
||||||
@ -7902,7 +7988,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||||||
} else {
|
} else {
|
||||||
tmp = load_reg(s, i);
|
tmp = load_reg(s, i);
|
||||||
}
|
}
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
j++;
|
j++;
|
||||||
@ -8161,20 +8247,20 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
if (insn & (1 << 20)) {
|
if (insn & (1 << 20)) {
|
||||||
/* ldrd */
|
/* ldrd */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rs, tmp);
|
store_reg(s, rs, tmp);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* strd */
|
/* strd */
|
||||||
tmp = load_reg(s, rs);
|
tmp = load_reg(s, rs);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
if (insn & (1 << 21)) {
|
if (insn & (1 << 21)) {
|
||||||
@ -8212,11 +8298,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tcg_gen_add_i32(addr, addr, tmp);
|
tcg_gen_add_i32(addr, addr, tmp);
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
} else { /* tbb */
|
} else { /* tbb */
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
tcg_gen_shli_i32(tmp, tmp, 1);
|
tcg_gen_shli_i32(tmp, tmp, 1);
|
||||||
@ -8253,13 +8339,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case 0: /* ldab */
|
case 0: /* ldab */
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1: /* ldah */
|
case 1: /* ldah */
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2: /* lda */
|
case 2: /* lda */
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -8269,13 +8355,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tmp = load_reg(s, rs);
|
tmp = load_reg(s, rs);
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case 0: /* stlb */
|
case 0: /* stlb */
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1: /* stlh */
|
case 1: /* stlh */
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2: /* stl */
|
case 2: /* stl */
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
abort();
|
||||||
@ -8303,10 +8389,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tcg_gen_addi_i32(addr, addr, -8);
|
tcg_gen_addi_i32(addr, addr, -8);
|
||||||
/* Load PC into tmp and CPSR into tmp2. */
|
/* Load PC into tmp and CPSR into tmp2. */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, 0);
|
gen_aa32_ld32u(tmp, addr, 0);
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
tmp2 = tcg_temp_new_i32();
|
tmp2 = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp2, addr, 0);
|
gen_aa32_ld32u(tmp2, addr, 0);
|
||||||
if (insn & (1 << 21)) {
|
if (insn & (1 << 21)) {
|
||||||
/* Base writeback. */
|
/* Base writeback. */
|
||||||
if (insn & (1 << 24)) {
|
if (insn & (1 << 24)) {
|
||||||
@ -8345,7 +8431,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
if (insn & (1 << 20)) {
|
if (insn & (1 << 20)) {
|
||||||
/* Load. */
|
/* Load. */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
if (i == 15) {
|
if (i == 15) {
|
||||||
gen_bx(s, tmp);
|
gen_bx(s, tmp);
|
||||||
} else if (i == rn) {
|
} else if (i == rn) {
|
||||||
@ -8357,7 +8443,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
} else {
|
} else {
|
||||||
/* Store. */
|
/* Store. */
|
||||||
tmp = load_reg(s, i);
|
tmp = load_reg(s, i);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
@ -9135,19 +9221,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, user);
|
gen_aa32_ld8u(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4:
|
||||||
tcg_gen_qemu_ld8s(tmp, addr, user);
|
gen_aa32_ld8s(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, user);
|
gen_aa32_ld16u(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 5:
|
case 5:
|
||||||
tcg_gen_qemu_ld16s(tmp, addr, user);
|
gen_aa32_ld16s(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, user);
|
gen_aa32_ld32u(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
@ -9164,13 +9250,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||||||
tmp = load_reg(s, rs);
|
tmp = load_reg(s, rs);
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case 0:
|
case 0:
|
||||||
tcg_gen_qemu_st8(tmp, addr, user);
|
gen_aa32_st8(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
tcg_gen_qemu_st16(tmp, addr, user);
|
gen_aa32_st16(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
tcg_gen_qemu_st32(tmp, addr, user);
|
gen_aa32_st32(tmp, addr, user);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
@ -9307,7 +9393,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
addr = tcg_temp_new_i32();
|
addr = tcg_temp_new_i32();
|
||||||
tcg_gen_movi_i32(addr, val);
|
tcg_gen_movi_i32(addr, val);
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
break;
|
break;
|
||||||
@ -9510,28 +9596,28 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
|
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case 0: /* str */
|
case 0: /* str */
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 1: /* strh */
|
case 1: /* strh */
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 2: /* strb */
|
case 2: /* strb */
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 3: /* ldrsb */
|
case 3: /* ldrsb */
|
||||||
tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
|
gen_aa32_ld8s(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 4: /* ldr */
|
case 4: /* ldr */
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 5: /* ldrh */
|
case 5: /* ldrh */
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 6: /* ldrb */
|
case 6: /* ldrb */
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
case 7: /* ldrsh */
|
case 7: /* ldrsh */
|
||||||
tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
|
gen_aa32_ld16s(tmp, addr, IS_USER(s));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (op >= 3) { /* load */
|
if (op >= 3) { /* load */
|
||||||
@ -9553,12 +9639,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
@ -9575,12 +9661,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
gen_aa32_st8(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
@ -9597,12 +9683,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
gen_aa32_st16(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
@ -9618,12 +9704,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, rd, tmp);
|
store_reg(s, rd, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, rd);
|
tmp = load_reg(s, rd);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_temp_free_i32(addr);
|
tcg_temp_free_i32(addr);
|
||||||
@ -9691,12 +9777,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* pop */
|
/* pop */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
store_reg(s, i, tmp);
|
store_reg(s, i, tmp);
|
||||||
} else {
|
} else {
|
||||||
/* push */
|
/* push */
|
||||||
tmp = load_reg(s, i);
|
tmp = load_reg(s, i);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
/* advance to the next address. */
|
/* advance to the next address. */
|
||||||
@ -9708,13 +9794,13 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* pop pc */
|
/* pop pc */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
/* don't set the pc until the rest of the instruction
|
/* don't set the pc until the rest of the instruction
|
||||||
has completed */
|
has completed */
|
||||||
} else {
|
} else {
|
||||||
/* push lr */
|
/* push lr */
|
||||||
tmp = load_reg(s, 14);
|
tmp = load_reg(s, 14);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
@ -9840,7 +9926,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
if (insn & (1 << 11)) {
|
if (insn & (1 << 11)) {
|
||||||
/* load */
|
/* load */
|
||||||
tmp = tcg_temp_new_i32();
|
tmp = tcg_temp_new_i32();
|
||||||
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
||||||
if (i == rn) {
|
if (i == rn) {
|
||||||
loaded_var = tmp;
|
loaded_var = tmp;
|
||||||
} else {
|
} else {
|
||||||
@ -9849,7 +9935,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
|||||||
} else {
|
} else {
|
||||||
/* store */
|
/* store */
|
||||||
tmp = load_reg(s, i);
|
tmp = load_reg(s, i);
|
||||||
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
gen_aa32_st32(tmp, addr, IS_USER(s));
|
||||||
tcg_temp_free_i32(tmp);
|
tcg_temp_free_i32(tmp);
|
||||||
}
|
}
|
||||||
/* advance to the next address */
|
/* advance to the next address */
|
||||||
|
Loading…
Reference in New Issue
Block a user