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target/hppa: Generate illegal instruction exception for 64-bit instructions

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Qemu currently emulates a 32-bit CPU only, and crashes with this error
when it faces a 64-bit load (e.g.  "ldd 0(r26),r0") or a 64-bit store
(e.g. "std r26,0(r26)") instruction in the guest:

ERROR:../qemu/tcg/tcg-op.c:2822:tcg_canonicalize_memop: code should not be reached

Add checks for 64-bit sizes and generate an illegal instruction
exception if necessary.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Helge Deller 2022-09-28 20:49:13 +02:00
parent c15dc499cc
commit 0786a3b605
1 changed files with 10 additions and 2 deletions
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8
target/hppa/translate.c
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@ -2899,15 +2899,23 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
static bool trans_ld(DisasContext *ctx, arg_ldst *a) static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{ {
if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
return gen_illegal(ctx);
} else {
return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE); a->disp, a->sp, a->m, a->size | MO_TE);
} }
}
static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_st(DisasContext *ctx, arg_ldst *a)
{ {
assert(a->x == 0 && a->scale == 0); assert(a->x == 0 && a->scale == 0);
if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
return gen_illegal(ctx);
} else {
return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
} }
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{ {