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hw/intc: Update APLIC IDC after claiming iforce register

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Currently, QEMU only sets the iforce register to 0 and returns early
when claiming the iforce register. However, this may leave mip.meip
remains at 1 if a spurious external interrupt triggered by iforce
register is the only pending interrupt to be claimed, and the interrupt
cannot be lowered as expected.

This commit fixes this issue by calling riscv_aplic_idc_update() to
update the IDC status after the iforce register is claimed.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240321104951.12104-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2024-03-21 18:49:48 +08:00 committed by Alistair Francis
parent 0a11629c91
commit 078189b327
1 changed files with 1 additions and 0 deletions
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hw/intc/riscv_aplic.c
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@ -488,6 +488,7 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
if (!topi) {
aplic->iforce[idc] = 0;
riscv_aplic_idc_update(aplic, idc);
return 0;
}