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target/riscv: Fix typo of mimpid cpu option

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"mimpid" cpu option was mistyped to "mipid".

Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-05-23 23:31:46 +08:00 committed by Alistair Francis
parent bb06941f95
commit 075eeda931
3 changed files with 7 additions and 7 deletions
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4
target/riscv/cpu.c
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@ -37,7 +37,7 @@
#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
(QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MINOR << 8) | \
(QEMU_VERSION_MICRO)) (QEMU_VERSION_MICRO))
#define RISCV_CPU_MIPID RISCV_CPU_MARCHID #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
@ -869,7 +869,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),

2
target/riscv/cpu.h
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@ -408,7 +408,7 @@ struct RISCVCPUConfig {
uint32_t mvendorid; uint32_t mvendorid;
uint64_t marchid; uint64_t marchid;
uint64_t mipid; uint64_t mimpid;
/* Vendor-specific custom extensions */ /* Vendor-specific custom extensions */
bool ext_XVentanaCondOps; bool ext_XVentanaCondOps;

6
target/riscv/csr.c
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@ -674,13 +674,13 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static RISCVException read_mipid(CPURISCVState *env, int csrno, static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.mipid; *val = cpu->cfg.mimpid;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -3372,7 +3372,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Information Registers */ /* Machine Information Registers */
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
[CSR_MARCHID] = { "marchid", any, read_marchid }, [CSR_MARCHID] = { "marchid", any, read_marchid },
[CSR_MIMPID] = { "mimpid", any, read_mipid }, [CSR_MIMPID] = { "mimpid", any, read_mimpid },
[CSR_MHARTID] = { "mhartid", any, read_mhartid }, [CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,