ioport: use uint{32, 16, 8}_t for ioport value and pio_addr_t for ioport address.
Using int for cpu_{in, out}[bwl] is inconsistent with other part
because for address or value, uintN_t is used by other qemu part.
At least, softmmu, CPU{Read, Write}MemoryFunc, pci, target_phys_addr_t
and the callers of cpu_{in, out}[bwl]().
This patch removes the inconsistency.
IO port has its own address space so define pio_addr_t as uint32_t
because PCI io space width is 32bit.
And use uint{32, 16, 8}_t for ioport value.
Changing signedness of value might cause subtle issue. However
only a suspicious caller is kvm_handle_io() which is ok. And other callers
pass unsigned value in the first place.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Cc: Stuart Brady <sdbrady@ntlworld.com>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Samuel Thibault <samuel.thibault@gnu.org>
Cc: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Isaku Yamahata
Anthony Liguori
parent
fc7083b530
commit
07323531c1
@ -23,35 +23,38 @@
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#include "qemu-common.h"
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#include "ioport.h"
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void cpu_outb(CPUState *env, int addr, int val)
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void cpu_outb(CPUState *env, pio_addr_t addr, uint8_t val)
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{
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fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
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fprintf(stderr, "outb: port=0x%04"FMT_pioaddr", data=%02"PRIx8"\n",
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addr, val);
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}
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void cpu_outw(CPUState *env, int addr, int val)
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void cpu_outw(CPUState *env, pio_addr_t addr, uint16_t val)
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{
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fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
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fprintf(stderr, "outw: port=0x%04"FMT_pioaddr", data=%04"PRIx16"\n",
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addr, val);
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}
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void cpu_outl(CPUState *env, int addr, int val)
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void cpu_outl(CPUState *env, pio_addr_t addr, uint32_t val)
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{
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fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
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fprintf(stderr, "outl: port=0x%04"FMT_pioaddr", data=%08"PRIx32"\n",
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addr, val);
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}
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int cpu_inb(CPUState *env, int addr)
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uint8_t cpu_inb(CPUState *env, pio_addr_t addr)
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{
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fprintf(stderr, "inb: port=0x%04x\n", addr);
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fprintf(stderr, "inb: port=0x%04"FMT_pioaddr"\n", addr);
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return 0;
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}
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int cpu_inw(CPUState *env, int addr)
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uint16_t cpu_inw(CPUState *env, pio_addr_t addr)
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{
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fprintf(stderr, "inw: port=0x%04x\n", addr);
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fprintf(stderr, "inw: port=0x%04"FMT_pioaddr"\n", addr);
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return 0;
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}
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int cpu_inl(CPUState *env, int addr)
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uint32_t cpu_inl(CPUState *env, pio_addr_t addr)
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{
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fprintf(stderr, "inl: port=0x%04x\n", addr);
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fprintf(stderr, "inl: port=0x%04"FMT_pioaddr"\n", addr);
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return 0;
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}
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37
ioport.c
37
ioport.c
@ -136,7 +136,7 @@ static int ioport_bsize(int size, int *bsize)
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}
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/* size is the word size in byte */
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int register_ioport_read(int start, int length, int size,
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int register_ioport_read(pio_addr_t start, int length, int size,
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IOPortReadFunc *func, void *opaque)
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{
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int i, bsize;
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@ -155,7 +155,7 @@ int register_ioport_read(int start, int length, int size,
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}
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/* size is the word size in byte */
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int register_ioport_write(int start, int length, int size,
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int register_ioport_write(pio_addr_t start, int length, int size,
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IOPortWriteFunc *func, void *opaque)
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{
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int i, bsize;
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@ -173,7 +173,7 @@ int register_ioport_write(int start, int length, int size,
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return 0;
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}
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void isa_unassign_ioport(int start, int length)
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void isa_unassign_ioport(pio_addr_t start, int length)
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{
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int i;
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@ -192,9 +192,9 @@ void isa_unassign_ioport(int start, int length)
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/***********************************************************/
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void cpu_outb(CPUState *env, int addr, int val)
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void cpu_outb(CPUState *env, pio_addr_t addr, uint8_t val)
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{
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LOG_IOPORT("outb: %04x %02x\n", addr, val);
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LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
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ioport_write(0, addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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@ -202,9 +202,9 @@ void cpu_outb(CPUState *env, int addr, int val)
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#endif
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}
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void cpu_outw(CPUState *env, int addr, int val)
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void cpu_outw(CPUState *env, pio_addr_t addr, uint16_t val)
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{
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LOG_IOPORT("outw: %04x %04x\n", addr, val);
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LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
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ioport_write(1, addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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@ -212,9 +212,9 @@ void cpu_outw(CPUState *env, int addr, int val)
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#endif
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}
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void cpu_outl(CPUState *env, int addr, int val)
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void cpu_outl(CPUState *env, pio_addr_t addr, uint32_t val)
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{
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LOG_IOPORT("outl: %04x %08x\n", addr, val);
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LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
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ioport_write(2, addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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@ -222,11 +222,11 @@ void cpu_outl(CPUState *env, int addr, int val)
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#endif
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}
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int cpu_inb(CPUState *env, int addr)
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uint8_t cpu_inb(CPUState *env, pio_addr_t addr)
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{
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int val;
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uint8_t val;
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val = ioport_read(0, addr);
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LOG_IOPORT("inb : %04x %02x\n", addr, val);
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LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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env->last_io_time = cpu_get_time_fast();
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@ -234,11 +234,11 @@ int cpu_inb(CPUState *env, int addr)
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return val;
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}
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int cpu_inw(CPUState *env, int addr)
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uint16_t cpu_inw(CPUState *env, pio_addr_t addr)
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{
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int val;
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uint16_t val;
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val = ioport_read(1, addr);
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LOG_IOPORT("inw : %04x %04x\n", addr, val);
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LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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env->last_io_time = cpu_get_time_fast();
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@ -246,15 +246,14 @@ int cpu_inw(CPUState *env, int addr)
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return val;
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}
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int cpu_inl(CPUState *env, int addr)
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uint32_t cpu_inl(CPUState *env, pio_addr_t addr)
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{
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int val;
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uint32_t val;
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val = ioport_read(2, addr);
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LOG_IOPORT("inl : %04x %08x\n", addr, val);
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LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
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#ifdef CONFIG_KQEMU
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if (env)
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env->last_io_time = cpu_get_time_fast();
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#endif
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return val;
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}
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21
ioport.h
21
ioport.h
@ -26,6 +26,9 @@
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#include "qemu-common.h"
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typedef uint32_t pio_addr_t;
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#define FMT_pioaddr PRIx32
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#define MAX_IOPORTS (64 * 1024)
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#define IOPORTS_MASK (MAX_IOPORTS - 1)
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@ -33,22 +36,22 @@
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typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
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typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
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int register_ioport_read(int start, int length, int size,
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int register_ioport_read(pio_addr_t start, int length, int size,
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IOPortReadFunc *func, void *opaque);
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int register_ioport_write(int start, int length, int size,
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int register_ioport_write(pio_addr_t start, int length, int size,
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IOPortWriteFunc *func, void *opaque);
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void isa_unassign_ioport(int start, int length);
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void isa_unassign_ioport(pio_addr_t start, int length);
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/* NOTE: as these functions may be even used when there is an isa
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brige on non x86 targets, we always defined them */
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#if !defined(NO_CPU_IO_DEFS) && defined(NEED_CPU_H)
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void cpu_outb(CPUState *env, int addr, int val);
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void cpu_outw(CPUState *env, int addr, int val);
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void cpu_outl(CPUState *env, int addr, int val);
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int cpu_inb(CPUState *env, int addr);
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int cpu_inw(CPUState *env, int addr);
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int cpu_inl(CPUState *env, int addr);
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void cpu_outb(CPUState *env, pio_addr_t addr, uint8_t val);
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void cpu_outw(CPUState *env, pio_addr_t addr, uint16_t val);
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void cpu_outl(CPUState *env, pio_addr_t addr, uint32_t val);
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uint8_t cpu_inb(CPUState *env, pio_addr_t addr);
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uint16_t cpu_inw(CPUState *env, pio_addr_t addr);
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uint32_t cpu_inl(CPUState *env, pio_addr_t addr);
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#endif
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#endif /* IOPORT_H */
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