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target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache

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For cap_ppc_safe_cache to be set to workaround, we require both a l1d
cache flush instruction and private l1d cache.

On POWER8 don't require private l1d cache. This means a guest on a
POWER8 machine can make use of the cache flush workarounds.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Suraj Jitindar Singh 2018-06-12 15:16:29 +10:00 committed by David Gibson
parent 2ef2f16781
commit 072f416a53
1 changed files with 18 additions and 1 deletions
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19
target/ppc/kvm.c
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@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void)
return cap_mmu_hash_v3; return cap_mmu_hash_v3;
} }
static bool kvmppc_power8_host(void)
{
bool ret = false;
#ifdef TARGET_PPC64
{
uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
(base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
(base_pvr == CPU_POWERPC_POWER8_BASE);
}
#endif /* TARGET_PPC64 */
return ret;
}
static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
{ {
bool l1d_thread_priv_req = !kvmppc_power8_host();
if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
return 2; return 2;
} else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && } else if ((!l1d_thread_priv_req ||
c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
(c.character & c.character_mask (c.character & c.character_mask
& (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
return 1; return 1;