target/riscv: Expose properties for Zv* extensions
Expose Zve64d,Zvfh,Zvfhmin properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-15-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -101,6 +101,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
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ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
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ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
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ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
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ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
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ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
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ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
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ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
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ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
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@ -1126,6 +1129,7 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
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DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
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DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
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DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
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DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
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DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
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DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
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@ -1185,6 +1189,9 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
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DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
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DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
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DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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