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target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1

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The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
 * EL1 accesses
 * EL0 accesses, if the access is not UNDEFINED when the
   trap bit is 0

(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
HSTR_EL2 traps from EL0 are priority 15.)

However, we don't get this right for EL1 accesses which UNDEF because
the register doesn't exist at all or because its ri->access bits
non-configurably forbid the access.  At EL1, check for the HSTR_EL2
trap early, before either of these UNDEF reasons.

We have to retain the HSTR_EL2 check in access_check_cp_reg(),
because at EL0 any kind of UNDEF-to-EL1 (including "no such
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
takes precedence over the trap to EL2.  But we only need to do that
check for EL0 now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-01-30 18:24:42 +00:00
parent cccc104bbf
commit 049edada5e
2 changed files with 32 additions and 2 deletions
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6
target/arm/op_helper.c
View File

@ -658,7 +658,11 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
goto fail;
}
if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
/*
* HSTR_EL2 traps from EL1 are checked earlier, in generated code;
* we only need to check here for traps from EL0.
*/
if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
uint32_t mask = 1 << ri->crn;

28
target/arm/translate.c
View File

@ -4760,6 +4760,32 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
break;
}
if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
/*
* At EL1, check for a HSTR_EL2 trap, which must take precedence
* over the UNDEF for "no such register" or the UNDEF for "access
* permissions forbid this EL1 access". HSTR_EL2 traps from EL0
* only happen if the cpreg doesn't UNDEF at EL0, so we do those in
* access_check_cp_reg(), after the checks for whether the access
* configurably trapped to EL1.
*/
uint32_t maskbit = is64 ? crm : crn;
if (maskbit != 4 && maskbit != 14) {
/* T4 and T14 are RES0 so never cause traps */
TCGv_i32 t;
DisasLabel over = gen_disas_label(s);
t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
tcg_gen_andi_i32(t, t, 1u << maskbit);
tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
tcg_temp_free_i32(t);
gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
set_disas_label(s, over);
}
}
if (!ri) {
/*
* Unknown register; this might be a guest error or a QEMU
@ -4788,7 +4814,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
return;
}
if (s->hstr_active || ri->accessfn ||
if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
/*
* Emit code to perform further access permissions checks at