ahci: split realize and init
Do the init level tasks asap and the realize later (mainly when num_ports is available). This allows sub-class realize routines to work with the device post-init. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1a7c7b2b32e5ccf49373a5065da5ece89730d3ac.1445917756.git.crosthwaite.peter@gmail.com Signed-off-by: John Snow <jsnow@redhat.com>
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@ -1434,7 +1434,17 @@ static const IDEDMAOps ahci_dma_ops = {
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.cmd_done = ahci_cmd_done,
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};
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void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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void ahci_init(AHCIState *s, DeviceState *qdev)
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{
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s->container = qdev;
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/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
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memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
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"ahci", AHCI_MEM_BAR_SIZE);
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memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
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"ahci-idp", 32);
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}
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void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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{
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qemu_irq *irqs;
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int i;
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@ -1442,16 +1452,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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s->as = as;
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s->ports = ports;
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s->dev = g_new0(AHCIDevice, ports);
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s->container = qdev;
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ahci_reg_init(s);
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/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
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memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
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"ahci", AHCI_MEM_BAR_SIZE);
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memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
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"ahci-idp", 32);
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irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
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for (i = 0; i < s->ports; i++) {
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AHCIDevice *ad = &s->dev[i];
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@ -1646,17 +1648,24 @@ static void sysbus_ahci_reset(DeviceState *dev)
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ahci_reset(&s->ahci);
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}
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static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
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static void sysbus_ahci_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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SysbusAHCIState *s = SYSBUS_AHCI(dev);
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SysbusAHCIState *s = SYSBUS_AHCI(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);
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ahci_init(&s->ahci, DEVICE(obj));
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sysbus_init_mmio(sbd, &s->ahci.mem);
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sysbus_init_irq(sbd, &s->ahci.irq);
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}
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static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
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{
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SysbusAHCIState *s = SYSBUS_AHCI(dev);
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ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
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}
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static Property sysbus_ahci_properties[] = {
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DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
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DEFINE_PROP_END_OF_LIST(),
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@ -1677,6 +1686,7 @@ static const TypeInfo sysbus_ahci_info = {
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.name = TYPE_SYSBUS_AHCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SysbusAHCIState),
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.instance_init = sysbus_ahci_init,
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.class_init = sysbus_ahci_class_init,
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};
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@ -366,7 +366,8 @@ typedef struct SDBFIS {
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uint32_t payload;
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} QEMU_PACKED SDBFIS;
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void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
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void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
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void ahci_init(AHCIState *s, DeviceState *qdev);
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void ahci_uninit(AHCIState *s);
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void ahci_reset(AHCIState *s);
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10
hw/ide/ich.c
10
hw/ide/ich.c
@ -97,6 +97,13 @@ static void pci_ich9_reset(DeviceState *dev)
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ahci_reset(&d->ahci);
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}
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static void pci_ich9_ahci_init(Object *obj)
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{
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struct AHCIPCIState *d = ICH_AHCI(obj);
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ahci_init(&d->ahci, DEVICE(obj));
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}
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static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
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{
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struct AHCIPCIState *d;
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@ -104,7 +111,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
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uint8_t *sata_cap;
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d = ICH_AHCI(dev);
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ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
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ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
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pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
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@ -171,6 +178,7 @@ static const TypeInfo ich_ahci_info = {
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.name = TYPE_ICH9_AHCI,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(AHCIPCIState),
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.instance_init = pci_ich9_ahci_init,
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.class_init = ich_ahci_class_init,
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};
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