mirrors
/
qemu
mirror of https://gitlab.com/qemu-project/qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER 

TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.).  Rename to EDGE_TRIGGER to
make the code comprehensible without looking up the data structure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Christoffer Dall 2013-12-20 22:09:32 -08:00 committed by Peter Maydell
parent 7b1aa025bd
commit 04050c5c6a
4 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/intc/arm_gic.c
View File

@ -128,7 +128,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
if (level) { if (level) {
GIC_SET_LEVEL(irq, cm); GIC_SET_LEVEL(irq, cm);
if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
DPRINTF("Set %d pending mask %x\n", irq, target); DPRINTF("Set %d pending mask %x\n", irq, target);
GIC_SET_PENDING(irq, target); GIC_SET_PENDING(irq, target);
} }
@ -188,7 +188,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
return; /* No active IRQ. */ return; /* No active IRQ. */
/* Mark level triggered interrupts as pending if they are still /* Mark level triggered interrupts as pending if they are still
raised. */ raised. */
if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
DPRINTF("Set %d pending mask %x\n", irq, cm); DPRINTF("Set %d pending mask %x\n", irq, cm);
GIC_SET_PENDING(irq, cm); GIC_SET_PENDING(irq, cm);
@ -311,7 +311,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
if (GIC_TEST_MODEL(irq + i)) if (GIC_TEST_MODEL(irq + i))
res |= (1 << (i * 2)); res |= (1 << (i * 2));
if (GIC_TEST_TRIGGER(irq + i)) if (GIC_TEST_EDGE_TRIGGER(irq + i))
res |= (2 << (i * 2)); res |= (2 << (i * 2));
} }
} else if (offset < 0xfe0) { } else if (offset < 0xfe0) {
@ -386,7 +386,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
/* If a raised level triggered IRQ enabled then mark /* If a raised level triggered IRQ enabled then mark
is as pending. */ is as pending. */
if (GIC_TEST_LEVEL(irq + i, mask) if (GIC_TEST_LEVEL(irq + i, mask)
&& !GIC_TEST_TRIGGER(irq + i)) { && !GIC_TEST_EDGE_TRIGGER(irq + i)) {
DPRINTF("Set %d pending mask %x\n", irq + i, mask); DPRINTF("Set %d pending mask %x\n", irq + i, mask);
GIC_SET_PENDING(irq + i, mask); GIC_SET_PENDING(irq + i, mask);
} }
@ -478,9 +478,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
GIC_CLEAR_MODEL(irq + i); GIC_CLEAR_MODEL(irq + i);
} }
if (value & (2 << (i * 2))) { if (value & (2 << (i * 2))) {
GIC_SET_TRIGGER(irq + i); GIC_SET_EDGE_TRIGGER(irq + i);
} else { } else {
GIC_CLEAR_TRIGGER(irq + i); GIC_CLEAR_EDGE_TRIGGER(irq + i);
} }
} }
} else { } else {

4
hw/intc/arm_gic_common.c
View File

@ -51,7 +51,7 @@ static const VMStateDescription vmstate_gic_irq_state = {
VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(active, gic_irq_state),
VMSTATE_UINT8(level, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state),
VMSTATE_BOOL(model, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state),
VMSTATE_BOOL(trigger, gic_irq_state), VMSTATE_BOOL(edge_trigger, gic_irq_state),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -126,7 +126,7 @@ static void arm_gic_common_reset(DeviceState *dev)
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_ENABLED(i, ALL_CPU_MASK);
GIC_SET_TRIGGER(i); GIC_SET_EDGE_TRIGGER(i);
} }
if (s->num_cpu == 1) { if (s->num_cpu == 1) {
/* For uniprocessor GICs all interrupts always target the sole CPU */ /* For uniprocessor GICs all interrupts always target the sole CPU */

6
hw/intc/gic_internal.h
View File

@ -44,9 +44,9 @@
#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true #define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false #define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false
#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger #define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
s->priority1[irq][cpu] : \ s->priority1[irq][cpu] : \
s->priority2[(irq) - GIC_INTERNAL]) s->priority2[(irq) - GIC_INTERNAL])

2
include/hw/intc/arm_gic_common.h
View File

@ -37,7 +37,7 @@ typedef struct gic_irq_state {
uint8_t active; uint8_t active;
uint8_t level; uint8_t level;
bool model; /* 0 = N:N, 1 = 1:N */ bool model; /* 0 = N:N, 1 = 1:N */
bool trigger; /* nonzero = edge triggered. */ bool edge_trigger; /* true: edge-triggered, false: level-triggered */
} gic_irq_state; } gic_irq_state;
typedef struct GICState { typedef struct GICState {