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tcg/s390x: Introduce HostAddress

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Collect the 3 potential parts of the host address into a struct.
Reorg tcg_out_qemu_{ld,st}_direct to use it.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-23 21:28:57 +01:00
parent 01a3b5dead
commit 036547487b
1 changed files with 60 additions and 49 deletions
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109
tcg/s390x/tcg-target.c.inc
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@ -1606,58 +1606,64 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest,
tcg_out_call_int(s, dest); tcg_out_call_int(s, dest);
} }
typedef struct {
TCGReg base;
TCGReg index;
int disp;
} HostAddress;
static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp) HostAddress h)
{ {
switch (opc & (MO_SSIZE | MO_BSWAP)) { switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB: case MO_UB:
tcg_out_insn(s, RXY, LLGC, data, base, index, disp); tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp);
break; break;
case MO_SB: case MO_SB:
tcg_out_insn(s, RXY, LGB, data, base, index, disp); tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp);
break; break;
case MO_UW | MO_BSWAP: case MO_UW | MO_BSWAP:
/* swapped unsigned halfword load with upper bits zeroed */ /* swapped unsigned halfword load with upper bits zeroed */
tcg_out_insn(s, RXY, LRVH, data, base, index, disp); tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
tcg_out_ext16u(s, data, data); tcg_out_ext16u(s, data, data);
break; break;
case MO_UW: case MO_UW:
tcg_out_insn(s, RXY, LLGH, data, base, index, disp); tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp);
break; break;
case MO_SW | MO_BSWAP: case MO_SW | MO_BSWAP:
/* swapped sign-extended halfword load */ /* swapped sign-extended halfword load */
tcg_out_insn(s, RXY, LRVH, data, base, index, disp); tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
tcg_out_ext16s(s, TCG_TYPE_REG, data, data); tcg_out_ext16s(s, TCG_TYPE_REG, data, data);
break; break;
case MO_SW: case MO_SW:
tcg_out_insn(s, RXY, LGH, data, base, index, disp); tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp);
break; break;
case MO_UL | MO_BSWAP: case MO_UL | MO_BSWAP:
/* swapped unsigned int load with upper bits zeroed */ /* swapped unsigned int load with upper bits zeroed */
tcg_out_insn(s, RXY, LRV, data, base, index, disp); tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
tcg_out_ext32u(s, data, data); tcg_out_ext32u(s, data, data);
break; break;
case MO_UL: case MO_UL:
tcg_out_insn(s, RXY, LLGF, data, base, index, disp); tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp);
break; break;
case MO_SL | MO_BSWAP: case MO_SL | MO_BSWAP:
/* swapped sign-extended int load */ /* swapped sign-extended int load */
tcg_out_insn(s, RXY, LRV, data, base, index, disp); tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
tcg_out_ext32s(s, data, data); tcg_out_ext32s(s, data, data);
break; break;
case MO_SL: case MO_SL:
tcg_out_insn(s, RXY, LGF, data, base, index, disp); tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp);
break; break;
case MO_UQ | MO_BSWAP: case MO_UQ | MO_BSWAP:
tcg_out_insn(s, RXY, LRVG, data, base, index, disp); tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp);
break; break;
case MO_UQ: case MO_UQ:
tcg_out_insn(s, RXY, LG, data, base, index, disp); tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp);
break; break;
default: default:
@ -1666,44 +1672,44 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
} }
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp) HostAddress h)
{ {
switch (opc & (MO_SIZE | MO_BSWAP)) { switch (opc & (MO_SIZE | MO_BSWAP)) {
case MO_UB: case MO_UB:
if (disp >= 0 && disp < 0x1000) { if (h.disp >= 0 && h.disp < 0x1000) {
tcg_out_insn(s, RX, STC, data, base, index, disp); tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp);
} else { } else {
tcg_out_insn(s, RXY, STCY, data, base, index, disp); tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp);
} }
break; break;
case MO_UW | MO_BSWAP: case MO_UW | MO_BSWAP:
tcg_out_insn(s, RXY, STRVH, data, base, index, disp); tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp);
break; break;
case MO_UW: case MO_UW:
if (disp >= 0 && disp < 0x1000) { if (h.disp >= 0 && h.disp < 0x1000) {
tcg_out_insn(s, RX, STH, data, base, index, disp); tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp);
} else { } else {
tcg_out_insn(s, RXY, STHY, data, base, index, disp); tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp);
} }
break; break;
case MO_UL | MO_BSWAP: case MO_UL | MO_BSWAP:
tcg_out_insn(s, RXY, STRV, data, base, index, disp); tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp);
break; break;
case MO_UL: case MO_UL:
if (disp >= 0 && disp < 0x1000) { if (h.disp >= 0 && h.disp < 0x1000) {
tcg_out_insn(s, RX, ST, data, base, index, disp); tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp);
} else { } else {
tcg_out_insn(s, RXY, STY, data, base, index, disp); tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp);
} }
break; break;
case MO_UQ | MO_BSWAP: case MO_UQ | MO_BSWAP:
tcg_out_insn(s, RXY, STRVG, data, base, index, disp); tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp);
break; break;
case MO_UQ: case MO_UQ:
tcg_out_insn(s, RXY, STG, data, base, index, disp); tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp);
break; break;
default: default:
@ -1883,20 +1889,23 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
return tcg_out_fail_alignment(s, l); return tcg_out_fail_alignment(s, l);
} }
static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg)
TCGReg *index_reg, tcg_target_long *disp)
{ {
TCGReg index;
int disp;
if (TARGET_LONG_BITS == 32) { if (TARGET_LONG_BITS == 32) {
tcg_out_ext32u(s, TCG_TMP0, *addr_reg); tcg_out_ext32u(s, TCG_TMP0, addr_reg);
*addr_reg = TCG_TMP0; addr_reg = TCG_TMP0;
} }
if (guest_base < 0x80000) { if (guest_base < 0x80000) {
*index_reg = TCG_REG_NONE; index = TCG_REG_NONE;
*disp = guest_base; disp = guest_base;
} else { } else {
*index_reg = TCG_GUEST_BASE_REG; index = TCG_GUEST_BASE_REG;
*disp = 0; disp = 0;
} }
return (HostAddress){ .base = addr_reg, .index = index, .disp = disp };
} }
#endif /* CONFIG_SOFTMMU */ #endif /* CONFIG_SOFTMMU */
@ -1904,31 +1913,32 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
MemOpIdx oi, TCGType data_type) MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
HostAddress h;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi); unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr; tcg_insn_unit *label_ptr;
TCGReg base_reg;
base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); h.base = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
h.index = TCG_REG_R2;
h.disp = 0;
tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
label_ptr = s->code_ptr; label_ptr = s->code_ptr;
s->code_ptr += 1; s->code_ptr += 1;
tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); tcg_out_qemu_ld_direct(s, opc, data_reg, h);
add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
s->code_ptr, label_ptr); s->code_ptr, label_ptr);
#else #else
TCGReg index_reg;
tcg_target_long disp;
unsigned a_bits = get_alignment_bits(opc); unsigned a_bits = get_alignment_bits(opc);
if (a_bits) { if (a_bits) {
tcg_out_test_alignment(s, true, addr_reg, a_bits); tcg_out_test_alignment(s, true, addr_reg, a_bits);
} }
tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); h = tcg_prepare_user_ldst(s, addr_reg);
tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); tcg_out_qemu_ld_direct(s, opc, data_reg, h);
#endif #endif
} }
@ -1936,31 +1946,32 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
MemOpIdx oi, TCGType data_type) MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
HostAddress h;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi); unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr; tcg_insn_unit *label_ptr;
TCGReg base_reg;
base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); h.base = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
h.index = TCG_REG_R2;
h.disp = 0;
tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
label_ptr = s->code_ptr; label_ptr = s->code_ptr;
s->code_ptr += 1; s->code_ptr += 1;
tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); tcg_out_qemu_st_direct(s, opc, data_reg, h);
add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
s->code_ptr, label_ptr); s->code_ptr, label_ptr);
#else #else
TCGReg index_reg;
tcg_target_long disp;
unsigned a_bits = get_alignment_bits(opc); unsigned a_bits = get_alignment_bits(opc);
if (a_bits) { if (a_bits) {
tcg_out_test_alignment(s, false, addr_reg, a_bits); tcg_out_test_alignment(s, false, addr_reg, a_bits);
} }
tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); h = tcg_prepare_user_ldst(s, addr_reg);
tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); tcg_out_qemu_st_direct(s, opc, data_reg, h);
#endif #endif
} }