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disas/riscv: Add Zb[abcs] instructions

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With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:16 +02:00 committed by Alistair Francis
parent 9916ea3c97
commit 02c1b569a1
1 changed files with 154 additions and 3 deletions
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157
disas/riscv.c
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@ -478,6 +478,49 @@ typedef enum {
rv_op_fsflags = 316, rv_op_fsflags = 316,
rv_op_fsrmi = 317, rv_op_fsrmi = 317,
rv_op_fsflagsi = 318, rv_op_fsflagsi = 318,
rv_op_bseti = 319,
rv_op_bclri = 320,
rv_op_binvi = 321,
rv_op_bexti = 322,
rv_op_rori = 323,
rv_op_clz = 324,
rv_op_ctz = 325,
rv_op_cpop = 326,
rv_op_sext_h = 327,
rv_op_sext_b = 328,
rv_op_xnor = 329,
rv_op_orn = 330,
rv_op_andn = 331,
rv_op_rol = 332,
rv_op_ror = 333,
rv_op_sh1add = 334,
rv_op_sh2add = 335,
rv_op_sh3add = 336,
rv_op_sh1add_uw = 337,
rv_op_sh2add_uw = 338,
rv_op_sh3add_uw = 339,
rv_op_clmul = 340,
rv_op_clmulr = 341,
rv_op_clmulh = 342,
rv_op_min = 343,
rv_op_minu = 344,
rv_op_max = 345,
rv_op_maxu = 346,
rv_op_clzw = 347,
rv_op_ctzw = 348,
rv_op_cpopw = 349,
rv_op_slli_uw = 350,
rv_op_add_uw = 351,
rv_op_rolw = 352,
rv_op_rorw = 353,
rv_op_rev8 = 354,
rv_op_zext_h = 355,
rv_op_roriw = 356,
rv_op_orc_b = 357,
rv_op_bset = 358,
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
} rv_op; } rv_op;
/* structures */ /* structures */
@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] = {
{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
{ "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
}; };
/* CSR names */ /* CSR names */
@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0: op = rv_op_addi; break; case 0: op = rv_op_addi; break;
case 1: case 1:
switch (((inst >> 27) & 0b11111)) { switch (((inst >> 27) & 0b11111)) {
case 0: op = rv_op_slli; break; case 0b00000: op = rv_op_slli; break;
case 0b00101: op = rv_op_bseti; break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_clz; break;
case 0b0000001: op = rv_op_ctz; break;
case 0b0000010: op = rv_op_cpop; break;
/* 0b0000011 */
case 0b0000100: op = rv_op_sext_b; break;
case 0b0000101: op = rv_op_sext_h; break;
}
break;
} }
break; break;
case 2: op = rv_op_slti; break; case 2: op = rv_op_slti; break;
@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 4: op = rv_op_xori; break; case 4: op = rv_op_xori; break;
case 5: case 5:
switch (((inst >> 27) & 0b11111)) { switch (((inst >> 27) & 0b11111)) {
case 0: op = rv_op_srli; break; case 0b00000: op = rv_op_srli; break;
case 8: op = rv_op_srai; break; case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
case 0b01100: op = rv_op_rori; break;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
}
break;
} }
break; break;
case 6: op = rv_op_ori; break; case 6: op = rv_op_ori; break;
@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1: case 1:
switch (((inst >> 25) & 0b1111111)) { switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_slliw; break; case 0: op = rv_op_slliw; break;
case 4: op = rv_op_slli_uw; break;
case 48:
switch ((inst >> 20) & 0b11111) {
case 0b00000: op = rv_op_clzw; break;
case 0b00001: op = rv_op_ctzw; break;
case 0b00010: op = rv_op_cpopw; break;
}
break;
} }
break; break;
case 5: case 5:
switch (((inst >> 25) & 0b1111111)) { switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_srliw; break; case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break; case 32: op = rv_op_sraiw; break;
case 48: op = rv_op_roriw; break;
} }
break; break;
} }
@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 13: op = rv_op_divu; break; case 13: op = rv_op_divu; break;
case 14: op = rv_op_rem; break; case 14: op = rv_op_rem; break;
case 15: op = rv_op_remu; break; case 15: op = rv_op_remu; break;
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
}
break;
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
case 44: op = rv_op_min; break;
case 45: op = rv_op_minu; break;
case 46: op = rv_op_max; break;
case 47: op = rv_op_maxu; break;
case 130: op = rv_op_sh1add; break;
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
case 256: op = rv_op_sub; break; case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break; case 261: op = rv_op_sra; break;
case 262: op = rv_op_orn; break;
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
} }
break; break;
case 13: op = rv_op_lui; break; case 13: op = rv_op_lui; break;
@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 13: op = rv_op_divuw; break; case 13: op = rv_op_divuw; break;
case 14: op = rv_op_remw; break; case 14: op = rv_op_remw; break;
case 15: op = rv_op_remuw; break; case 15: op = rv_op_remuw; break;
case 32: op = rv_op_add_uw; break;
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
case 132: op = rv_op_sh2add_uw; break;
case 134: op = rv_op_sh3add_uw; break;
case 256: op = rv_op_subw; break; case 256: op = rv_op_subw; break;
case 261: op = rv_op_sraw; break; case 261: op = rv_op_sraw; break;
case 385: op = rv_op_rolw; break;
case 389: op = rv_op_rorw; break;
} }
break; break;
case 16: case 16: