qemu-lock.h: Remove non-pthreads spinlock implementations
Since configure guarantees us that we have pthreads on all hosts except mingw (which doesn't support a USER_ONLY config), we can and should use the pthread_mutex based implementation of spin_lock() and spin_unlock() in all USER_ONLY cases. This means that all the inline-native-assembly code supporting the "USER_ONLY but not USE_NPTL" case can go away. The not-USER_ONLY case remains as empty implementations; there is no change in behaviour here. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell
Aurelien Jarno
parent
322fd48afb
commit
02615337ef
210
qemu-lock.h
210
qemu-lock.h
@ -15,15 +15,11 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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/* Locking primitives. Most of this code should be redundant -
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system emulation doesn't need/use locking, NPTL userspace uses
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pthread mutexes, and non-NPTL userspace isn't threadsafe anyway.
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In either case a spinlock is probably the wrong kind of lock.
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Spinlocks are only good if you know annother CPU has the lock and is
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likely to release it soon. In environments where you have more threads
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than physical CPUs (the extreme case being a single CPU host) a spinlock
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simply wastes CPU until the OS decides to preempt it. */
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#if defined(CONFIG_USE_NPTL)
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/* configure guarantees us that we have pthreads on any host except
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* mingw32, which doesn't support any of the user-only targets.
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* So we can simply assume we have pthread mutexes here.
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*/
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#if defined(CONFIG_USER_ONLY)
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#include <pthread.h>
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#define spin_lock pthread_mutex_lock
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@ -33,198 +29,15 @@
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#else
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#if defined(__hppa__)
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typedef int spinlock_t[4];
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#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
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static inline void resetlock (spinlock_t *p)
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{
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(*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
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}
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#else
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/* Empty implementations, on the theory that system mode emulation
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* is single-threaded. This means that these functions should only
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* be used from code run in the TCG cpu thread, and cannot protect
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* data structures which might also be accessed from the IO thread
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* or from signal handlers.
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*/
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typedef int spinlock_t;
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#define SPIN_LOCK_UNLOCKED 0
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static inline void resetlock (spinlock_t *p)
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{
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*p = SPIN_LOCK_UNLOCKED;
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}
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#endif
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#if defined(_ARCH_PPC)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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" lwarx %0,0,%1\n"
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" xor. %0,%3,%0\n"
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" bne $+12\n"
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" stwcx. %2,0,%1\n"
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" bne- $-16\n"
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0)
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: "cr0", "memory");
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return ret;
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}
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#elif defined(__i386__)
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static inline int testandset (int *p)
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{
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long int readval = 0;
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__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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: "+m" (*p), "+a" (readval)
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: "r" (1)
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: "cc");
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return readval;
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}
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#elif defined(__x86_64__)
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static inline int testandset (int *p)
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{
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long int readval = 0;
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__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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: "+m" (*p), "+a" (readval)
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: "r" (1)
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: "cc");
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return readval;
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}
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#elif defined(__s390__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b"
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: "=&d" (ret)
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: "r" (1), "a" (p), "0" (*p)
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: "cc", "memory" );
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return ret;
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}
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#elif defined(__alpha__)
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static inline int testandset (int *p)
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{
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int ret;
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unsigned long one;
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n"
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" stl_c %2,%1\n"
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" beq %2,1f\n"
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".subsection 2\n"
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"1: br 0b\n"
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".previous"
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: "=r" (ret), "=m" (*p), "=r" (one)
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: "m" (*p));
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return ret;
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}
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#elif defined(__sparc__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret)
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: "r" (p)
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: "memory");
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return (ret ? 1 : 0);
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}
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#elif defined(__arm__)
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static inline int testandset (int *spinlock)
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{
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register unsigned int ret;
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__asm__ __volatile__("swp %0, %1, [%2]"
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: "=r"(ret)
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: "0"(1), "r"(spinlock));
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return ret;
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}
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#elif defined(__mc68000)
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static inline int testandset (int *p)
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{
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char ret;
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__asm__ __volatile__("tas %1; sne %0"
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: "=r" (ret)
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: "m" (p)
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: "cc","memory");
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return ret;
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}
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#elif defined(__hppa__)
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/* Because malloc only guarantees 8-byte alignment for malloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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static inline void *ldcw_align (void *p) {
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unsigned long a = (unsigned long)p;
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a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
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return (void *)a;
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}
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static inline int testandset (spinlock_t *p)
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{
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unsigned int ret;
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p = ldcw_align(p);
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__asm__ __volatile__("ldcw 0(%1),%0"
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: "=r" (ret)
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: "r" (p)
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: "memory" );
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return !ret;
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}
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#elif defined(__ia64)
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#include <ia64intrin.h>
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static inline int testandset (int *p)
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{
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return __sync_lock_test_and_set (p, 1);
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}
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#elif defined(__mips__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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" .set push \n"
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" .set noat \n"
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" .set mips2 \n"
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"1: li $1, 1 \n"
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" ll %0, %1 \n"
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" sc $1, %1 \n"
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" beqz $1, 1b \n"
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" .set pop "
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: "=r" (ret), "+R" (*p)
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:
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: "memory");
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return ret;
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}
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#else
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#error unimplemented CPU support
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#endif
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#if defined(CONFIG_USER_ONLY)
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static inline void spin_lock(spinlock_t *lock)
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{
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while (testandset(lock));
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}
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static inline void spin_unlock(spinlock_t *lock)
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{
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resetlock(lock);
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}
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#else
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static inline void spin_lock(spinlock_t *lock)
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{
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}
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@ -232,6 +45,5 @@ static inline void spin_lock(spinlock_t *lock)
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static inline void spin_unlock(spinlock_t *lock)
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{
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}
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#endif
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#endif
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