target-ppc: implement xscpsgnqp instruction
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -612,9 +612,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
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#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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int xa; \
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int xt = rD(ctx->opcode) + 32; \
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int xb = rB(ctx->opcode) + 32; \
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TCGv_i64 xbh, xbl, sgm; \
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TCGv_i64 xah, xbh, xbl, sgm; \
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\
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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@ -636,6 +637,14 @@ static void glue(gen_, name)(DisasContext *ctx) \
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case OP_NEG: \
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tcg_gen_xor_i64(xbh, xbh, sgm); \
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break; \
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case OP_CPSGN: \
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xah = tcg_temp_new_i64(); \
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xa = rA(ctx->opcode) + 32; \
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tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
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tcg_gen_andc_i64(xbh, xbh, sgm); \
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tcg_gen_or_i64(xbh, xbh, xah); \
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tcg_temp_free_i64(xah); \
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break; \
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} \
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tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
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tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
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@ -647,6 +656,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
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VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
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VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
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VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
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#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext * ctx) \
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@ -99,6 +99,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
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GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
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GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
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GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
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GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
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GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
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GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
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