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target-i386/helper: remove EDX macro

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Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson  <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
liguang 2013-05-28 16:21:02 +08:00 committed by Blue Swirl
parent a416561005
commit 00f5e6f21e
6 changed files with 28 additions and 30 deletions
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2
target-i386/cpu.h
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@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env)
? MMU_KSMAP_IDX : MMU_KERNEL_IDX; ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
} }
#undef EDX
#define EDX (env->regs[R_EDX])
#undef ESP #undef ESP
#define ESP (env->regs[R_ESP]) #define ESP (env->regs[R_ESP])
#undef EBP #undef EBP

24
target-i386/int_helper.c
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@ -81,7 +81,7 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0)
{ {
unsigned int num, den, q, r; unsigned int num, den, q, r;
num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16); num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
den = (t0 & 0xffff); den = (t0 & 0xffff);
if (den == 0) { if (den == 0) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
@ -93,14 +93,14 @@ void helper_divw_AX(CPUX86State *env, target_ulong t0)
q &= 0xffff; q &= 0xffff;
r = (num % den) & 0xffff; r = (num % den) & 0xffff;
env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q; env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
EDX = (EDX & ~0xffff) | r; env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
} }
void helper_idivw_AX(CPUX86State *env, target_ulong t0) void helper_idivw_AX(CPUX86State *env, target_ulong t0)
{ {
int num, den, q, r; int num, den, q, r;
num = (env->regs[R_EAX] & 0xffff) | ((EDX & 0xffff) << 16); num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
den = (int16_t)t0; den = (int16_t)t0;
if (den == 0) { if (den == 0) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
@ -112,7 +112,7 @@ void helper_idivw_AX(CPUX86State *env, target_ulong t0)
q &= 0xffff; q &= 0xffff;
r = (num % den) & 0xffff; r = (num % den) & 0xffff;
env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q; env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
EDX = (EDX & ~0xffff) | r; env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
} }
void helper_divl_EAX(CPUX86State *env, target_ulong t0) void helper_divl_EAX(CPUX86State *env, target_ulong t0)
@ -120,7 +120,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
unsigned int den, r; unsigned int den, r;
uint64_t num, q; uint64_t num, q;
num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32); num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0; den = t0;
if (den == 0) { if (den == 0) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
@ -131,7 +131,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
env->regs[R_EAX] = (uint32_t)q; env->regs[R_EAX] = (uint32_t)q;
EDX = (uint32_t)r; env->regs[R_EDX] = (uint32_t)r;
} }
void helper_idivl_EAX(CPUX86State *env, target_ulong t0) void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
@ -139,7 +139,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
int den, r; int den, r;
int64_t num, q; int64_t num, q;
num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32); num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
den = t0; den = t0;
if (den == 0) { if (den == 0) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
@ -150,7 +150,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
env->regs[R_EAX] = (uint32_t)q; env->regs[R_EAX] = (uint32_t)q;
EDX = (uint32_t)r; env->regs[R_EDX] = (uint32_t)r;
} }
/* bcd */ /* bcd */
@ -382,12 +382,12 @@ void helper_divq_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
r0 = env->regs[R_EAX]; r0 = env->regs[R_EAX];
r1 = EDX; r1 = env->regs[R_EDX];
if (div64(&r0, &r1, t0)) { if (div64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
env->regs[R_EAX] = r0; env->regs[R_EAX] = r0;
EDX = r1; env->regs[R_EDX] = r1;
} }
void helper_idivq_EAX(CPUX86State *env, target_ulong t0) void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
@ -398,12 +398,12 @@ void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
r0 = env->regs[R_EAX]; r0 = env->regs[R_EAX];
r1 = EDX; r1 = env->regs[R_EDX];
if (idiv64(&r0, &r1, t0)) { if (idiv64(&r0, &r1, t0)) {
raise_exception(env, EXCP00_DIVZ); raise_exception(env, EXCP00_DIVZ);
} }
env->regs[R_EAX] = r0; env->regs[R_EAX] = r0;
EDX = r1; env->regs[R_EDX] = r1;
} }
#endif #endif

8
target-i386/mem_helper.c
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@ -45,13 +45,13 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP); eflags = cpu_cc_compute_all(env, CC_OP);
d = cpu_ldq_data(env, a0); d = cpu_ldq_data(env, a0);
if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) { if (d == (((uint64_t)env->regs[R_EDX] << 32) | (uint32_t)env->regs[R_EAX])) {
cpu_stq_data(env, a0, ((uint64_t)env->regs[R_ECX] << 32) | (uint32_t)env->regs[R_EBX]); cpu_stq_data(env, a0, ((uint64_t)env->regs[R_ECX] << 32) | (uint32_t)env->regs[R_EBX]);
eflags |= CC_Z; eflags |= CC_Z;
} else { } else {
/* always do the store */ /* always do the store */
cpu_stq_data(env, a0, d); cpu_stq_data(env, a0, d);
EDX = (uint32_t)(d >> 32); env->regs[R_EDX] = (uint32_t)(d >> 32);
env->regs[R_EAX] = (uint32_t)d; env->regs[R_EAX] = (uint32_t)d;
eflags &= ~CC_Z; eflags &= ~CC_Z;
} }
@ -70,7 +70,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
eflags = cpu_cc_compute_all(env, CC_OP); eflags = cpu_cc_compute_all(env, CC_OP);
d0 = cpu_ldq_data(env, a0); d0 = cpu_ldq_data(env, a0);
d1 = cpu_ldq_data(env, a0 + 8); d1 = cpu_ldq_data(env, a0 + 8);
if (d0 == env->regs[R_EAX] && d1 == EDX) { if (d0 == env->regs[R_EAX] && d1 == env->regs[R_EDX]) {
cpu_stq_data(env, a0, env->regs[R_EBX]); cpu_stq_data(env, a0, env->regs[R_EBX]);
cpu_stq_data(env, a0 + 8, env->regs[R_ECX]); cpu_stq_data(env, a0 + 8, env->regs[R_ECX]);
eflags |= CC_Z; eflags |= CC_Z;
@ -78,7 +78,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
/* always do the store */ /* always do the store */
cpu_stq_data(env, a0, d0); cpu_stq_data(env, a0, d0);
cpu_stq_data(env, a0 + 8, d1); cpu_stq_data(env, a0 + 8, d1);
EDX = d1; env->regs[R_EDX] = d1;
env->regs[R_EAX] = d0; env->regs[R_EAX] = d0;
eflags &= ~CC_Z; eflags &= ~CC_Z;
} }

8
target-i386/misc_helper.c
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@ -126,7 +126,7 @@ void helper_cpuid(CPUX86State *env)
env->regs[R_EAX] = eax; env->regs[R_EAX] = eax;
env->regs[R_EBX] = ebx; env->regs[R_EBX] = ebx;
env->regs[R_ECX] = ecx; env->regs[R_ECX] = ecx;
EDX = edx; env->regs[R_EDX] = edx;
} }
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -235,7 +235,7 @@ void helper_rdtsc(CPUX86State *env)
val = cpu_get_tsc(env) + env->tsc_offset; val = cpu_get_tsc(env) + env->tsc_offset;
env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EAX] = (uint32_t)(val);
EDX = (uint32_t)(val >> 32); env->regs[R_EDX] = (uint32_t)(val >> 32);
} }
void helper_rdtscp(CPUX86State *env) void helper_rdtscp(CPUX86State *env)
@ -271,7 +271,7 @@ void helper_wrmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1); cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32); val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
switch ((uint32_t)env->regs[R_ECX]) { switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS: case MSR_IA32_SYSENTER_CS:
@ -549,7 +549,7 @@ void helper_rdmsr(CPUX86State *env)
break; break;
} }
env->regs[R_EAX] = (uint32_t)(val); env->regs[R_EAX] = (uint32_t)(val);
EDX = (uint32_t)(val >> 32); env->regs[R_EDX] = (uint32_t)(val >> 32);
} }
#endif #endif

8
target-i386/seg_helper.c
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@ -326,7 +326,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags); cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX); cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP); cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP); cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
@ -342,7 +342,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags); cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX); cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP); cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP); cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
@ -398,7 +398,7 @@ static void switch_tss(CPUX86State *env, int tss_selector,
/* XXX: what to do in 16 bit case? */ /* XXX: what to do in 16 bit case? */
env->regs[R_EAX] = new_regs[0]; env->regs[R_EAX] = new_regs[0];
env->regs[R_ECX] = new_regs[1]; env->regs[R_ECX] = new_regs[1];
EDX = new_regs[2]; env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3]; env->regs[R_EBX] = new_regs[3];
ESP = new_regs[4]; ESP = new_regs[4];
EBP = new_regs[5]; EBP = new_regs[5];
@ -2289,7 +2289,7 @@ void helper_sysexit(CPUX86State *env, int dflag)
DESC_W_MASK | DESC_A_MASK); DESC_W_MASK | DESC_A_MASK);
} }
ESP = env->regs[R_ECX]; ESP = env->regs[R_ECX];
EIP = EDX; EIP = env->regs[R_EDX];
} }
target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)

8
target-i386/smm_helper.c
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@ -84,7 +84,7 @@ void do_smm_enter(CPUX86State *env)
stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]); stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]); stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(sm_state + 0x7fe8, EDX); stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]); stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, ESP); stq_phys(sm_state + 0x7fd8, ESP);
stq_phys(sm_state + 0x7fd0, EBP); stq_phys(sm_state + 0x7fd0, EBP);
@ -114,7 +114,7 @@ void do_smm_enter(CPUX86State *env)
stl_phys(sm_state + 0x7fe4, EBP); stl_phys(sm_state + 0x7fe4, EBP);
stl_phys(sm_state + 0x7fe0, ESP); stl_phys(sm_state + 0x7fe0, ESP);
stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]); stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
stl_phys(sm_state + 0x7fd8, EDX); stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]); stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]); stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
stl_phys(sm_state + 0x7fcc, env->dr[6]); stl_phys(sm_state + 0x7fcc, env->dr[6]);
@ -215,7 +215,7 @@ void helper_rsm(CPUX86State *env)
env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8); env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0); env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
EDX = ldq_phys(sm_state + 0x7fe8); env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0); env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
ESP = ldq_phys(sm_state + 0x7fd8); ESP = ldq_phys(sm_state + 0x7fd8);
EBP = ldq_phys(sm_state + 0x7fd0); EBP = ldq_phys(sm_state + 0x7fd0);
@ -249,7 +249,7 @@ void helper_rsm(CPUX86State *env)
EBP = ldl_phys(sm_state + 0x7fe4); EBP = ldl_phys(sm_state + 0x7fe4);
ESP = ldl_phys(sm_state + 0x7fe0); ESP = ldl_phys(sm_state + 0x7fe0);
env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc); env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
EDX = ldl_phys(sm_state + 0x7fd8); env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4); env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0); env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
env->dr[6] = ldl_phys(sm_state + 0x7fcc); env->dr[6] = ldl_phys(sm_state + 0x7fcc);