ppc/xive2: Change context/ring specific functions to be generic
Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -114,7 +114,7 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
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}
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}
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void xive_tctx_reset_os_signal(XiveTCTX *tctx)
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void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring)
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{
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/*
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* Lower the External interrupt. Used when pulling an OS
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@ -122,7 +122,7 @@ void xive_tctx_reset_os_signal(XiveTCTX *tctx)
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* context. It should be raised again when re-pushing the OS
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* context.
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*/
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qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS));
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qemu_irq_lower(xive_tctx_output(tctx, ring));
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}
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static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
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@ -424,7 +424,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
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xive_tctx_set_os_cam(tctx, qw1w2_new);
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xive_tctx_reset_os_signal(tctx);
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xive_tctx_reset_signal(tctx, TM_QW1_OS);
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return qw1w2;
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}
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@ -270,13 +270,14 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)
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* the NVP by changing the H bit while the context is enabled
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*/
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static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
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uint8_t nvp_blk, uint32_t nvp_idx)
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static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
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uint8_t nvp_blk, uint32_t nvp_idx,
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uint8_t ring)
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{
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CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
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uint32_t pir = env->spr_cb[SPR_PIR].default_value;
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Xive2Nvp nvp;
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uint8_t *regs = &tctx->regs[TM_QW1_OS];
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uint8_t *regs = &tctx->regs[ring];
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if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
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@ -321,8 +322,8 @@ static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
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xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
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}
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static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
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uint32_t *nvp_idx, bool *vo, bool *ho)
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static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk,
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uint32_t *nvp_idx, bool *vo, bool *ho)
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{
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*nvp_blk = xive2_nvp_blk(cam);
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*nvp_idx = xive2_nvp_idx(cam);
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@ -330,7 +331,6 @@ static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
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*ho = !!(cam & TM2_QW1W2_HO);
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}
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/*
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* Encode the HW CAM line with 7bit or 8bit thread id. The thread id
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* width and block id width is configurable at the IC level.
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@ -363,7 +363,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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bool vo;
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bool do_save;
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xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);
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xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);
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if (!vo) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
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@ -375,10 +375,10 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
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if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
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xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx);
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xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, TM_QW1_OS);
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}
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xive_tctx_reset_os_signal(tctx);
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xive_tctx_reset_signal(tctx, TM_QW1_OS);
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return qw1w2;
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}
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@ -573,7 +573,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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bool vo;
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bool do_restore;
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xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
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xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
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/* First update the thead context */
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
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@ -533,7 +533,7 @@ Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
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void xive_tctx_reset(XiveTCTX *tctx);
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void xive_tctx_destroy(XiveTCTX *tctx);
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void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
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void xive_tctx_reset_os_signal(XiveTCTX *tctx);
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void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
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/*
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* KVM XIVE device helpers
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