target-arm: Provide syndrome information for MMU faults
Set up the required syndrome information when we detect an MMU fault. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: split out from exception handling patch, tweaked to bring in line with how we create other kinds of syndrome information] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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@ -3696,6 +3696,8 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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target_ulong page_size;
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int prot;
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int ret, is_user;
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uint32_t syn;
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bool same_el = (arm_current_pl(env) != 0);
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is_user = mmu_idx == MMU_USER_IDX;
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ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
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@ -3708,14 +3710,24 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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return 0;
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}
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/* AArch64 syndrome does not have an LPAE bit */
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syn = ret & ~(1 << 9);
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/* For insn and data aborts we assume there is no instruction syndrome
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* information; this is always true for exceptions reported to EL1.
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*/
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if (access_type == 2) {
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syn = syn_insn_abort(same_el, 0, 0, syn);
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cs->exception_index = EXCP_PREFETCH_ABORT;
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} else {
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syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
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if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
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ret |= (1 << 11);
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}
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cs->exception_index = EXCP_DATA_ABORT;
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}
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env->exception.syndrome = syn;
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env->exception.vaddress = address;
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env->exception.fsr = ret;
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return 1;
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@ -188,4 +188,17 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
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{
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return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (ea << 9) | (s1ptw << 7) | fsc;
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}
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static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
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int wnr, int fsc)
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{
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return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
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}
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#endif
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