ARM PCI host qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook
parent
0e058a8a6a
commit
0027b06d0e
@ -26,7 +26,4 @@ extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
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/* arm_sysctl.c */
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void arm_sysctl_init(uint32_t base, uint32_t sys_id);
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/* versatile_pci.c */
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PCIBus *pci_vpb_init(qemu_irq *pic, int realview);
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#endif
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@ -32,6 +32,7 @@ static void realview_init(ram_addr_t ram_size,
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CPUState *env;
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ram_addr_t ram_offset;
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qemu_irq *pic;
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DeviceState *dev;
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PCIBus *pci_bus;
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NICInfo *nd;
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int n;
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@ -100,7 +101,9 @@ static void realview_init(ram_addr_t ram_size,
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sysbus_create_simple("pl031", 0x10017000, pic[10]);
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pci_bus = pci_vpb_init(pic + 48, 1);
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dev = sysbus_create_varargs("realview_pci", 0x60000000,
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pic[48], pic[49], pic[50], pic[51], NULL);
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pci_bus = qdev_get_child_bus(dev, "pci");
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if (usb_enabled) {
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usb_ohci_init_pci(pci_bus, 3, -1);
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}
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@ -1,15 +1,21 @@
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/*
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* ARM Versatile/PB PCI host controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Copyright (c) 2006-2009 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the LGPL.
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "pci.h"
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#include "primecell.h"
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typedef struct {
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SysBusDevice busdev;
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qemu_irq irq[4];
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int realview;
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int mem_config;
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} PCIVPBState;
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static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
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{
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@ -89,44 +95,51 @@ static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
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qemu_set_irq(pic[irq_num], level);
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}
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PCIBus *pci_vpb_init(qemu_irq *pic, int realview)
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static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
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{
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PCIBus *s;
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PCIDevice *d;
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int mem_config;
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uint32_t base;
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const char * name;
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qemu_irq *irqs;
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int i;
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irqs = qemu_mallocz(sizeof(qemu_irq) * 4);
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for (i = 0; i < 4; i++) {
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irqs[i] = pic[i];
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}
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if (realview) {
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base = 0x60000000;
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name = "RealView EB PCI Controller";
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} else {
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base = 0x40000000;
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name = "Versatile/PB PCI Controller";
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}
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s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, irqs, 11 << 3, 4);
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/* ??? Register memory space. */
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mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
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pci_vpb_config_write, s);
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PCIVPBState *s = (PCIVPBState *)dev;
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/* Selfconfig area. */
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cpu_register_physical_memory(base + 0x01000000, 0x1000000, mem_config);
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cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
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/* Normal config area. */
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cpu_register_physical_memory(base + 0x02000000, 0x1000000, mem_config);
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cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
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d = pci_register_device(s, name, sizeof(PCIDevice), -1, NULL, NULL);
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if (realview) {
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if (s->realview) {
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/* IO memory area. */
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isa_mmio_init(base + 0x03000000, 0x00100000);
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}
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}
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static void pci_vpb_init(SysBusDevice *dev)
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{
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PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
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PCIBus *bus;
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int i;
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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bus = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
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11 << 3, 4);
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qdev_attach_child_bus(&dev->qdev, "pci", bus);
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/* ??? Register memory space. */
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s->mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
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pci_vpb_config_write, bus);
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sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
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pci_create_simple(bus, -1, "versatile_pci_host");
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}
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static void pci_realview_init(SysBusDevice *dev)
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{
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PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
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s->realview = 1;
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pci_vpb_init(dev);
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}
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static void versatile_pci_host_init(PCIDevice *d)
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{
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX);
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/* Both boards have the same device ID. Oh well. */
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30);
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@ -138,6 +151,15 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int realview)
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d->config[0x09] = 0x00; // programming i/f
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pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
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d->config[0x0D] = 0x10; // latency_timer
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return s;
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}
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static void versatile_pci_register_devices(void)
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{
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sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
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sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
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pci_realview_init);
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pci_qdev_register("versatile_pci_host", sizeof(PCIDevice),
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versatile_pci_host_init);
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}
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device_init(versatile_pci_register_devices)
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@ -199,7 +199,10 @@ static void versatile_init(ram_addr_t ram_size,
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sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
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sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
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pci_bus = pci_vpb_init(sic + 27, 0);
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dev = sysbus_create_varargs("versatile_pci", 0x40000000,
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sic[27], sic[28], sic[29], sic[30], NULL);
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pci_bus = qdev_get_child_bus(dev, "pci");
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/* The Versatile PCI bridge does not provide access to PCI IO space,
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so many of the qemu PCI devices are not useable. */
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for(n = 0; n < nb_nics; n++) {
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