2018-03-02 15:31:10 +03:00
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/*
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* RISC-V Emulation Helpers for QEMU.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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/* Exceptions processing helpers */
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2019-01-15 02:58:23 +03:00
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void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
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2018-03-02 15:31:10 +03:00
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uint32_t exception, uintptr_t pc)
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{
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2019-03-23 05:11:37 +03:00
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CPUState *cs = env_cpu(env);
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2018-03-02 15:31:10 +03:00
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qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
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cs->exception_index = exception;
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cpu_loop_exit_restore(cs, pc);
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}
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void helper_raise_exception(CPURISCVState *env, uint32_t exception)
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{
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, exception, 0);
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2018-03-02 15:31:10 +03:00
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}
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target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
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target_ulong csr)
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{
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2019-01-05 02:23:55 +03:00
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target_ulong val = 0;
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2020-08-12 22:13:46 +03:00
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int ret = riscv_csrrw(env, csr, &val, src, -1);
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if (ret < 0) {
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riscv_raise_exception(env, -ret, GETPC());
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2019-01-05 02:23:55 +03:00
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}
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return val;
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2018-03-02 15:31:10 +03:00
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}
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target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
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target_ulong csr, target_ulong rs1_pass)
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{
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2019-01-05 02:23:55 +03:00
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target_ulong val = 0;
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2020-08-12 22:13:46 +03:00
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int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
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if (ret < 0) {
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riscv_raise_exception(env, -ret, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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2019-01-05 02:23:55 +03:00
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return val;
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2018-03-02 15:31:10 +03:00
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}
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target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
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target_ulong csr, target_ulong rs1_pass)
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{
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2019-01-05 02:23:55 +03:00
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target_ulong val = 0;
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2020-08-12 22:13:46 +03:00
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int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
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if (ret < 0) {
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riscv_raise_exception(env, -ret, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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2019-01-05 02:23:55 +03:00
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return val;
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2018-03-02 15:31:10 +03:00
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}
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#ifndef CONFIG_USER_ONLY
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target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
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{
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2020-02-01 04:02:33 +03:00
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target_ulong prev_priv, prev_virt, mstatus;
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2018-03-02 15:31:10 +03:00
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if (!(env->priv >= PRV_S)) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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target_ulong retpc = env->sepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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2020-05-05 23:04:50 +03:00
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if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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2019-01-15 02:58:08 +03:00
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}
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2020-08-12 22:13:49 +03:00
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if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_VTSR)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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}
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2020-02-01 04:02:33 +03:00
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mstatus = env->mstatus;
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if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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/* We support Hypervisor extensions and virtulisation is disabled */
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target_ulong hstatus = env->hstatus;
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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prev_virt = get_field(hstatus, HSTATUS_SPV);
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2020-08-12 22:13:33 +03:00
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hstatus = set_field(hstatus, HSTATUS_SPV, 0);
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mstatus = set_field(mstatus, MSTATUS_SPP, 0);
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2020-02-01 04:02:33 +03:00
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mstatus = set_field(mstatus, SSTATUS_SIE,
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get_field(mstatus, SSTATUS_SPIE));
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mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
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env->mstatus = mstatus;
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env->hstatus = hstatus;
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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} else {
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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2020-05-05 23:04:50 +03:00
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mstatus = set_field(mstatus, MSTATUS_SIE,
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get_field(mstatus, MSTATUS_SPIE));
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2020-02-01 04:02:33 +03:00
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mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
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mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
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env->mstatus = mstatus;
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}
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2019-01-15 02:58:23 +03:00
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riscv_cpu_set_mode(env, prev_priv);
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2018-03-02 15:31:10 +03:00
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return retpc;
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}
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target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
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{
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if (!(env->priv >= PRV_M)) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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target_ulong retpc = env->mepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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2018-03-02 15:31:10 +03:00
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}
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target_ulong mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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2020-02-01 04:03:08 +03:00
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target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
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2020-05-05 23:04:50 +03:00
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mstatus = set_field(mstatus, MSTATUS_MIE,
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get_field(mstatus, MSTATUS_MPIE));
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2020-01-03 06:53:42 +03:00
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mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
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2018-03-02 15:31:10 +03:00
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mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
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2020-02-01 04:03:05 +03:00
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#ifdef TARGET_RISCV32
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env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
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#else
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2020-02-01 04:02:33 +03:00
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mstatus = set_field(mstatus, MSTATUS_MPV, 0);
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2020-02-01 04:03:05 +03:00
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#endif
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2019-01-05 02:23:55 +03:00
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env->mstatus = mstatus;
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2020-02-01 04:02:33 +03:00
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riscv_cpu_set_mode(env, prev_priv);
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if (riscv_has_ext(env, RVH)) {
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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}
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2018-03-02 15:31:10 +03:00
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return retpc;
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}
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void helper_wfi(CPURISCVState *env)
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{
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2019-03-23 05:11:37 +03:00
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CPUState *cs = env_cpu(env);
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2018-03-02 15:31:10 +03:00
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2020-02-01 04:02:28 +03:00
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if ((env->priv == PRV_S &&
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get_field(env->mstatus, MSTATUS_TW)) ||
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riscv_cpu_virt_enabled(env)) {
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2020-08-12 22:13:49 +03:00
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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2019-01-15 02:58:08 +03:00
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} else {
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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}
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2018-03-02 15:31:10 +03:00
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}
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void helper_tlb_flush(CPURISCVState *env)
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{
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2019-03-23 05:11:37 +03:00
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CPUState *cs = env_cpu(env);
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2019-04-01 22:12:07 +03:00
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if (!(env->priv >= PRV_S) ||
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(env->priv == PRV_S &&
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get_field(env->mstatus, MSTATUS_TVM))) {
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2019-01-15 02:58:23 +03:00
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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2020-08-12 22:13:49 +03:00
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} else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_VTVM)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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2019-01-15 02:58:08 +03:00
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} else {
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tlb_flush(cs);
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}
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2018-03-02 15:31:10 +03:00
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}
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2020-04-04 01:54:59 +03:00
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void helper_hyp_tlb_flush(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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2020-08-12 22:13:49 +03:00
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if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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}
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2020-04-04 01:54:59 +03:00
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if (env->priv == PRV_M ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
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tlb_flush(cs);
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return;
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}
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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2020-08-12 22:13:49 +03:00
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void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
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{
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if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
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get_field(env->mstatus, MSTATUS_TVM)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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helper_hyp_tlb_flush(env);
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}
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2020-08-12 22:13:19 +03:00
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target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
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target_ulong attrs, target_ulong memop)
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{
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if (env->priv == PRV_M ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_HU))) {
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target_ulong pte;
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riscv_cpu_set_two_stage_lookup(env, true);
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switch (memop) {
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case MO_SB:
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pte = cpu_ldsb_data_ra(env, address, GETPC());
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break;
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case MO_UB:
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pte = cpu_ldub_data_ra(env, address, GETPC());
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break;
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case MO_TESW:
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pte = cpu_ldsw_data_ra(env, address, GETPC());
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break;
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case MO_TEUW:
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pte = cpu_lduw_data_ra(env, address, GETPC());
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break;
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case MO_TESL:
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pte = cpu_ldl_data_ra(env, address, GETPC());
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break;
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case MO_TEUL:
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pte = cpu_ldl_data_ra(env, address, GETPC());
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break;
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case MO_TEQ:
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pte = cpu_ldq_data_ra(env, address, GETPC());
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break;
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default:
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g_assert_not_reached();
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}
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riscv_cpu_set_two_stage_lookup(env, false);
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return pte;
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}
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2020-08-12 22:13:49 +03:00
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if (riscv_cpu_virt_enabled(env)) {
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riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
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} else {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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2020-08-12 22:13:19 +03:00
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return 0;
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}
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void helper_hyp_store(CPURISCVState *env, target_ulong address,
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target_ulong val, target_ulong attrs, target_ulong memop)
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{
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if (env->priv == PRV_M ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
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(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
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get_field(env->hstatus, HSTATUS_HU))) {
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riscv_cpu_set_two_stage_lookup(env, true);
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switch (memop) {
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case MO_SB:
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case MO_UB:
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cpu_stb_data_ra(env, address, val, GETPC());
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break;
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case MO_TESW:
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case MO_TEUW:
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cpu_stw_data_ra(env, address, val, GETPC());
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break;
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|
case MO_TESL:
|
|
|
|
case MO_TEUL:
|
|
|
|
cpu_stl_data_ra(env, address, val, GETPC());
|
|
|
|
break;
|
|
|
|
case MO_TEQ:
|
|
|
|
cpu_stq_data_ra(env, address, val, GETPC());
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
|
|
|
riscv_cpu_set_two_stage_lookup(env, false);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-08-12 22:13:49 +03:00
|
|
|
if (riscv_cpu_virt_enabled(env)) {
|
|
|
|
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
|
|
|
|
} else {
|
|
|
|
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
|
|
|
}
|
2020-08-12 22:13:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
|
|
|
|
target_ulong attrs, target_ulong memop)
|
|
|
|
{
|
|
|
|
if (env->priv == PRV_M ||
|
|
|
|
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
|
|
|
|
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
|
|
|
|
get_field(env->hstatus, HSTATUS_HU))) {
|
|
|
|
target_ulong pte;
|
|
|
|
|
|
|
|
riscv_cpu_set_two_stage_lookup(env, true);
|
|
|
|
|
|
|
|
switch (memop) {
|
|
|
|
case MO_TEUL:
|
|
|
|
pte = cpu_ldub_data_ra(env, address, GETPC());
|
|
|
|
break;
|
|
|
|
case MO_TEUW:
|
|
|
|
pte = cpu_lduw_data_ra(env, address, GETPC());
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
|
|
|
riscv_cpu_set_two_stage_lookup(env, false);
|
|
|
|
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
2020-08-12 22:13:49 +03:00
|
|
|
if (riscv_cpu_virt_enabled(env)) {
|
|
|
|
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
|
|
|
|
} else {
|
|
|
|
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
|
|
|
}
|
2020-08-12 22:13:19 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-03-02 15:31:10 +03:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|