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qemu/hw/microblaze/xlnx-zynqmp-pmu.c

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xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
/*
* Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
*
* Copyright (C) 2017 Xilinx Inc
* Written by Alistair Francis <alistair.francis@xilinx.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "exec/address-spaces.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
#include "hw/boards.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "hw/qdev-properties.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
#include "cpu.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "boot.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
#include "hw/intc/xlnx-zynqmp-ipi.h"
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
#include "hw/intc/xlnx-pmu-iomod-intc.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
/* Define the PMU device */
#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
TYPE_XLNX_ZYNQMP_PMU_SOC)
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
};
static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
19, 20, 21, 22,
};
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
typedef struct XlnxZynqMPPMUSoCState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
MicroBlazeCPU cpu;
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
XlnxPMUIOIntc intc;
hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state The Inter Processor Interrupt is a block part of the SoC, not the "machine" (talking about machine is borderline with the PMU, since it is embedded into the ZynqMP SoC, but currentl QEMU doesn't support multi-arch cores). Move the IPI state to the SoC state, this will simplify the review of the next patch. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-12-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-07 19:34:11 +03:00
XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
} XlnxZynqMPPMUSoCState;
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
static void xlnx_zynqmp_pmu_soc_init(Object *obj)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' Valgrind complains: echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ "'arguments':{'typename':'xlnx,zynqmp-pmu-soc'}}" \ "{'execute': 'human-monitor-command', " \ "'arguments': {'command-line': 'info qtree'}}" | \ valgrind -q microblazeel-softmmu/qemu-system-microblazeel -M none,accel=qtest -qmp stdio [...] ==13605== Invalid read of size 8 ==13605== at 0x2AC69A: qdev_print (qdev-monitor.c:686) ==13605== by 0x2AC69A: qbus_print (qdev-monitor.c:719) ==13605== by 0x2591E8: handle_hmp_command (monitor.c:3446) Use the new object_initialize_child() and sysbus_init_child_obj() to fix the issue. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1531839343-13828-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-23 17:21:25 +03:00
object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
TYPE_MICROBLAZE_CPU, &error_abort, NULL);
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' Valgrind complains: echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ "'arguments':{'typename':'xlnx,zynqmp-pmu-soc'}}" \ "{'execute': 'human-monitor-command', " \ "'arguments': {'command-line': 'info qtree'}}" | \ valgrind -q microblazeel-softmmu/qemu-system-microblazeel -M none,accel=qtest -qmp stdio [...] ==13605== Invalid read of size 8 ==13605== at 0x2AC69A: qdev_print (qdev-monitor.c:686) ==13605== by 0x2AC69A: qbus_print (qdev-monitor.c:719) ==13605== by 0x2591E8: handle_hmp_command (monitor.c:3446) Use the new object_initialize_child() and sysbus_init_child_obj() to fix the issue. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1531839343-13828-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-23 17:21:25 +03:00
sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
TYPE_XLNX_PMU_IO_INTC);
hw/microblaze/zynqmp: Let the SoC manage the IPI devices The Inter Processor Interrupt is a block part of the SoC, not the "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform Management Unit", Power Domains and Islands). Move the IPI management from the machine to the SoC. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-13-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-07 19:34:12 +03:00
/* Create the IPI device */
for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script (then manually modified to use numbered IPI name) @use_sysbus_init_child_obj_missing_parent@ expression child_ptr; expression child_type; expression child_size; @@ - object_initialize(child_ptr, child_size, child_type); ... - qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default()); ... ?- object_unref(OBJECT(child_ptr)); + sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr, + child_size, child_type); We let the SoC adopt the IPI children. While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. This choice also matches when using sysbus_init_child_obj(), since its code is: void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); } Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-14-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-07 19:34:13 +03:00
char *name = g_strdup_printf("ipi%d", i);
sysbus_init_child_obj(obj, name, &s->ipi[i],
sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
g_free(name);
hw/microblaze/zynqmp: Let the SoC manage the IPI devices The Inter Processor Interrupt is a block part of the SoC, not the "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform Management Unit", Power Domains and Islands). Move the IPI management from the machine to the SoC. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-13-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-07 19:34:12 +03:00
}
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
Error *err = NULL;
object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
"base-vectors", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
&error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
&error_abort);
object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
&error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
&error_abort);
object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
&error_abort);
object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
&error_abort);
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
hw/microblaze/zynqmp: Let the SoC manage the IPI devices The Inter Processor Interrupt is a block part of the SoC, not the "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform Management Unit", Power Domains and Islands). Move the IPI management from the machine to the SoC. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-13-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-07 19:34:12 +03:00
/* Connect the IPI device */
for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
}
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = xlnx_zynqmp_pmu_soc_realize;
}
static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
.name = TYPE_XLNX_ZYNQMP_PMU_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(XlnxZynqMPPMUSoCState),
.instance_init = xlnx_zynqmp_pmu_soc_init,
.class_init = xlnx_zynqmp_pmu_soc_class_init,
};
static void xlnx_zynqmp_pmu_soc_register_types(void)
{
type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
}
type_init(xlnx_zynqmp_pmu_soc_register_types)
/* Define the PMU Machine */
static void xlnx_zynqmp_pmu_init(MachineState *machine)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
/* Create the ROM */
memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
pmu_rom);
/* Create the RAM */
memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
machine->ram_size, &error_fatal);
memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
pmu_ram);
/* Create the PMU device */
object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
&error_abort);
object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
machine->ram_size,
machine->initrd_filename,
machine->dtb,
NULL);
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
mc->desc = "Xilinx ZynqMP PMU machine";
mc->init = xlnx_zynqmp_pmu_init;
}
DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
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