qemu/tests/tcg/xtensa/test_s32c1i.S

#include "macros.inc"

test_suite s32c1i

#if XCHAL_HAVE_S32C1I

test s32c1i_nowrite
#if XCHAL_HW_VERSION >= 230000
    movi    a2, 0x29
    wsr     a2, atomctl
#endif
    movi    a2, 1f
    movi    a3, 1
    wsr     a3, scompare1
    movi    a1, 2
    s32c1i  a1, a2, 0
    assert  ne, a1, a3
    l32i    a1, a2, 0
    assert  eqi, a1, 3

.data
.align 4
1:
    .word   3
.text
test_end

test s32c1i_write
#if XCHAL_HW_VERSION >= 230000
    movi    a2, 0x29
    wsr     a2, atomctl
#endif
    movi    a2, 1f
    movi    a3, 3
    wsr     a3, scompare1
    movi    a1, 2
    s32c1i  a1, a2, 0
    assert  eq, a1, a3
    l32i    a1, a2, 0
    assert  eqi, a1, 2

.data
.align 4
1:
    .word   3
.text
test_end

#endif

test_suite_end
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2014-02-10 20:20:52 +04:00			`#include "macros.inc"`
target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> 2012-12-05 07:15:26 +04:00
			`test_suite s32c1i`

tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2019-02-18 18:15:10 +03:00			`#if XCHAL_HAVE_S32C1I`

target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> 2012-12-05 07:15:26 +04:00			`test s32c1i_nowrite`
tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2019-02-18 18:15:10 +03:00			`#if XCHAL_HW_VERSION >= 230000`
			`movi a2, 0x29`
			`wsr a2, atomctl`
			`#endif`
target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> 2012-12-05 07:15:26 +04:00			`movi a2, 1f`
			`movi a3, 1`
			`wsr a3, scompare1`
			`movi a1, 2`
			`s32c1i a1, a2, 0`
			`assert ne, a1, a3`
			`l32i a1, a2, 0`
			`assert eqi, a1, 3`

			`.data`
			`.align 4`
			`1:`
			`.word 3`
			`.text`
			`test_end`

			`test s32c1i_write`
tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2019-02-18 18:15:10 +03:00			`#if XCHAL_HW_VERSION >= 230000`
			`movi a2, 0x29`
			`wsr a2, atomctl`
			`#endif`
target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> 2012-12-05 07:15:26 +04:00			`movi a2, 1f`
			`movi a3, 3`
			`wsr a3, scompare1`
			`movi a1, 2`
			`s32c1i a1, a2, 0`
			`assert eq, a1, a3`
			`l32i a1, a2, 0`
			`assert eqi, a1, 2`

			`.data`
			`.align 4`
			`1:`
			`.word 3`
			`.text`
			`test_end`

tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2019-02-18 18:15:10 +03:00			`#endif`

target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> 2012-12-05 07:15:26 +04:00			`test_suite_end`