2003-05-25 20:46:15 +04:00
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/*
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* internal execution defines for qemu
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2007-09-17 01:08:06 +04:00
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*
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2003-05-25 20:46:15 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-05-25 20:46:15 +04:00
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*/
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2016-06-29 14:47:03 +03:00
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#ifndef EXEC_ALL_H
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#define EXEC_ALL_H
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2009-01-14 22:00:36 +03:00
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2019-08-12 08:23:31 +03:00
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#include "cpu.h"
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2016-03-15 15:16:36 +03:00
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#include "exec/tb-context.h"
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2019-05-17 14:36:10 +03:00
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#ifdef CONFIG_TCG
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2018-11-04 00:40:22 +03:00
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#include "exec/cpu_ldst.h"
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2019-05-17 14:36:10 +03:00
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#endif
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2020-08-19 14:17:19 +03:00
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#include "sysemu/cpu-timers.h"
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2009-01-14 22:00:36 +03:00
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2003-06-16 00:05:50 +04:00
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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2008-11-11 16:41:01 +03:00
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#define DEBUG_DISAS
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2003-06-16 00:05:50 +04:00
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2010-03-12 19:54:58 +03:00
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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type. */
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#if defined(CONFIG_USER_ONLY)
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2010-03-13 02:23:29 +03:00
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typedef abi_ulong tb_page_addr_t;
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2017-07-14 00:18:15 +03:00
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#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
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2010-03-12 19:54:58 +03:00
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#else
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typedef ram_addr_t tb_page_addr_t;
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2017-07-14 00:18:15 +03:00
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#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
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2010-03-12 19:54:58 +03:00
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#endif
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2012-12-17 21:20:00 +04:00
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#include "qemu/log.h"
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2003-06-16 00:05:50 +04:00
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2019-04-16 09:54:54 +03:00
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
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void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
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2015-09-02 01:51:12 +03:00
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target_ulong *data);
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2008-04-28 04:32:32 +04:00
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2008-02-01 13:50:11 +03:00
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void cpu_gen_init(void);
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2017-11-13 16:55:27 +03:00
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/**
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* cpu_restore_state:
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* @cpu: the vCPU state is to be restore to
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* @searched_pc: the host PC the fault occurred at
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2018-04-09 12:13:20 +03:00
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* @will_exit: true if the TB executed will be interrupted after some
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cpu adjustments. Required for maintaining the correct
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icount valus
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2017-11-13 16:55:27 +03:00
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* @return: true if state was restored, false otherwise
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*
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* Attempt to restore the state for a fault occurring in translated
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* code. If the searched_pc is not in translated code no state is
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* restored and the function returns false.
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*/
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2018-04-09 12:13:20 +03:00
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bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
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2012-12-05 00:16:07 +04:00
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2016-05-17 17:18:04 +03:00
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void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
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2013-09-01 19:21:47 +04:00
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void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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2013-09-01 19:43:17 +04:00
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TranslationBlock *tb_gen_code(CPUState *cpu,
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2016-04-07 20:19:22 +03:00
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target_ulong pc, target_ulong cs_base,
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uint32_t flags,
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2008-06-29 05:03:05 +04:00
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int cflags);
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2016-07-25 12:59:19 +03:00
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2013-08-27 19:52:12 +04:00
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void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
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2015-07-10 12:57:02 +03:00
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void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
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2016-06-30 08:12:55 +03:00
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void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
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2015-04-22 15:15:48 +03:00
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s390x/tcg: MVCL: Exit to main loop if requested
MVCL is interruptible and we should check for interrupts and process
them after writing back the variables to the registers. Let's check
for any exit requests and exit to the main loop. Introduce a new helper
function for that: cpu_loop_exit_requested().
When booting Fedora 30, I can see a handful of these exits and it seems
to work reliable. Also, Richard explained why this works correctly even
when MVCL is called via EXECUTE:
(1) TB with EXECUTE runs, at address Ae
- env->psw_addr stored with Ae.
- helper_ex() runs, memory address Am computed
from D2a(X2a,B2a) or from psw.addr+RI2.
- env->ex_value stored with memory value modified by R1a
(2) TB of executee runs,
- env->ex_value stored with 0.
- helper_mvcl() runs, using and updating R1b, R1b+1, R2b, R2b+1.
(3a) helper_mvcl() completes,
- TB of executee continues, psw.addr += ilen.
- Next instruction is the one following EXECUTE.
(3b) helper_mvcl() exits to main loop,
- cpu_loop_exit_restore() unwinds psw.addr = Ae.
- Next instruction is the EXECUTE itself...
- goto 1.
As the PoP mentiones that an interruptible instruction called via EXECUTE
should avoid modifying storage/registers that are used by EXECUTE itself,
it is fine to retrigger EXECUTE.
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-10-01 21:03:54 +03:00
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/**
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* cpu_loop_exit_requested:
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* @cpu: The CPU state to be tested
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*
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* Indicate if somebody asked for a return of the CPU to the main loop
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* (e.g., via cpu_exit() or cpu_interrupt()).
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*
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* This is helpful for architectures that support interruptible
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* instructions. After writing back all state to registers/memory, this
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* call can be used to check if it makes sense to return to the main loop
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* or to continue executing the interruptible instruction.
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*/
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static inline bool cpu_loop_exit_requested(CPUState *cpu)
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{
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2020-09-23 13:56:46 +03:00
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return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
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s390x/tcg: MVCL: Exit to main loop if requested
MVCL is interruptible and we should check for interrupts and process
them after writing back the variables to the registers. Let's check
for any exit requests and exit to the main loop. Introduce a new helper
function for that: cpu_loop_exit_requested().
When booting Fedora 30, I can see a handful of these exits and it seems
to work reliable. Also, Richard explained why this works correctly even
when MVCL is called via EXECUTE:
(1) TB with EXECUTE runs, at address Ae
- env->psw_addr stored with Ae.
- helper_ex() runs, memory address Am computed
from D2a(X2a,B2a) or from psw.addr+RI2.
- env->ex_value stored with memory value modified by R1a
(2) TB of executee runs,
- env->ex_value stored with 0.
- helper_mvcl() runs, using and updating R1b, R1b+1, R2b, R2b+1.
(3a) helper_mvcl() completes,
- TB of executee continues, psw.addr += ilen.
- Next instruction is the one following EXECUTE.
(3b) helper_mvcl() exits to main loop,
- cpu_loop_exit_restore() unwinds psw.addr = Ae.
- Next instruction is the EXECUTE itself...
- goto 1.
As the PoP mentiones that an interruptible instruction called via EXECUTE
should avoid modifying storage/registers that are used by EXECUTE itself,
it is fine to retrigger EXECUTE.
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-10-01 21:03:54 +03:00
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}
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2012-04-09 20:50:52 +04:00
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#if !defined(CONFIG_USER_ONLY)
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2015-10-01 17:29:50 +03:00
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void cpu_reloading_memory_map(void);
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2016-01-21 17:15:04 +03:00
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/**
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* cpu_address_space_init:
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* @cpu: CPU to add this address space to
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* @asidx: integer index of this address space
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2017-11-23 12:23:32 +03:00
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* @prefix: prefix to be used as name of address space
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* @mr: the root memory region of address space
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2016-01-21 17:15:04 +03:00
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*
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* Add the specified address space to the CPU's cpu_ases list.
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* The address space added with @asidx 0 is the one used for the
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* convenience pointer cpu->as.
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* The target-specific code which registers ASes is responsible
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* for defining what semantics address space 0, 1, 2, etc have.
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*
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2016-01-21 17:15:04 +03:00
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* Before the first call to this function, the caller must set
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* cpu->num_ases to the total number of address spaces it needs
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* to support.
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*
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2016-01-21 17:15:04 +03:00
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* Note that with KVM only one address space is supported.
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*/
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2017-11-23 12:23:32 +03:00
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void cpu_address_space_init(CPUState *cpu, int asidx,
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const char *prefix, MemoryRegion *mr);
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2017-07-03 13:12:21 +03:00
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#endif
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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2012-04-09 20:50:52 +04:00
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/* cputlb.c */
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2018-10-09 20:45:54 +03:00
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/**
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* tlb_init - initialize a CPU's TLB
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* @cpu: CPU whose TLB should be initialized
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*/
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void tlb_init(CPUState *cpu);
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2020-06-12 22:02:26 +03:00
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/**
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* tlb_destroy - destroy a CPU's TLB
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* @cpu: CPU whose TLB should be destroyed
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*/
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void tlb_destroy(CPUState *cpu);
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2015-08-25 17:45:09 +03:00
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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2013-09-04 03:29:02 +04:00
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void tlb_flush_page(CPUState *cpu, target_ulong addr);
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2017-02-23 21:29:22 +03:00
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/**
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* tlb_flush_page_all_cpus:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
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/**
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* tlb_flush_page_all_cpus_synced:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all MMU
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* indexes like tlb_flush_page_all_cpus except the source vCPUs work
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* is scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
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2015-08-25 17:45:09 +03:00
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/**
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* tlb_flush:
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* @cpu: CPU whose TLB should be flushed
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*
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2016-11-14 17:17:28 +03:00
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* Flush the entire TLB for the specified CPU. Most CPU architectures
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* allow the implementation to drop entries from the TLB at any time
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* so this is generally safe. If more selective flushing is required
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* use one of the other functions for efficiency.
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2015-08-25 17:45:09 +03:00
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*/
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2016-11-14 17:17:28 +03:00
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void tlb_flush(CPUState *cpu);
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2017-02-23 21:29:22 +03:00
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/**
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* tlb_flush_all_cpus:
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* @cpu: src CPU of the flush
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*/
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void tlb_flush_all_cpus(CPUState *src_cpu);
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/**
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* tlb_flush_all_cpus_synced:
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* @cpu: src CPU of the flush
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*
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* Like tlb_flush_all_cpus except this except the source vCPUs work is
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* scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_all_cpus_synced(CPUState *src_cpu);
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2015-08-25 17:45:09 +03:00
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/**
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* tlb_flush_page_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
|
2017-02-23 21:29:19 +03:00
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* @idxmap: bitmap of MMU indexes to flush
|
2015-08-25 17:45:09 +03:00
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*
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* Flush one page from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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2017-02-23 21:29:19 +03:00
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void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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2017-02-23 21:29:22 +03:00
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/**
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* tlb_flush_page_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified MMU
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* indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
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* vCPUs work is scheduled as safe work meaning all flushes will be
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* complete once the source vCPUs safe work is complete. This will
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* depend on when the guests translation ends the TB.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
|
2015-08-25 17:45:09 +03:00
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/**
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* tlb_flush_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
|
2017-02-23 21:29:22 +03:00
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* @wait: If true ensure synchronisation by exiting the cpu_loop
|
2017-02-23 21:29:19 +03:00
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* @idxmap: bitmap of MMU indexes to flush
|
2015-08-25 17:45:09 +03:00
|
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*
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* Flush all entries from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
|
2017-02-23 21:29:19 +03:00
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
|
2017-02-23 21:29:22 +03:00
|
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/**
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* tlb_flush_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from all TLBs of all CPUs, for the specified
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* MMU indexes.
|
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*/
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void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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|
|
* Flush all entries from all TLBs of all CPUs, for the specified
|
|
|
|
* MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
|
|
|
|
* vCPUs work is scheduled as safe work meaning all flushes will be
|
|
|
|
* complete once the source vCPUs safe work is complete. This will
|
|
|
|
* depend on when the guests translation ends the TB.
|
|
|
|
*/
|
|
|
|
void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
|
2020-10-17 00:07:53 +03:00
|
|
|
|
|
|
|
/**
|
|
|
|
* tlb_flush_page_bits_by_mmuidx
|
|
|
|
* @cpu: CPU whose TLB should be flushed
|
|
|
|
* @addr: virtual address of page to be flushed
|
|
|
|
* @idxmap: bitmap of mmu indexes to flush
|
|
|
|
* @bits: number of significant bits in address
|
|
|
|
*
|
|
|
|
* Similar to tlb_flush_page_mask, but with a bitmap of indexes.
|
|
|
|
*/
|
|
|
|
void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
|
|
|
|
uint16_t idxmap, unsigned bits);
|
|
|
|
|
|
|
|
/* Similarly, with broadcast and syncing. */
|
|
|
|
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
|
|
|
|
uint16_t idxmap, unsigned bits);
|
|
|
|
void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
|
|
|
|
(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
|
|
|
|
|
2016-01-21 17:15:04 +03:00
|
|
|
/**
|
|
|
|
* tlb_set_page_with_attrs:
|
|
|
|
* @cpu: CPU to add this TLB entry for
|
|
|
|
* @vaddr: virtual address of page to add entry for
|
|
|
|
* @paddr: physical address of the page
|
|
|
|
* @attrs: memory transaction attributes
|
|
|
|
* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
|
|
|
|
* @mmu_idx: MMU index to insert TLB entry for
|
|
|
|
* @size: size of the page in bytes
|
|
|
|
*
|
|
|
|
* Add an entry to this CPU's TLB (a mapping from virtual address
|
|
|
|
* @vaddr to physical address @paddr) with the specified memory
|
|
|
|
* transaction attributes. This is generally called by the target CPU
|
|
|
|
* specific code after it has been called through the tlb_fill()
|
|
|
|
* entry point and performed a successful page table walk to find
|
|
|
|
* the physical address and attributes for the virtual address
|
|
|
|
* which provoked the TLB miss.
|
|
|
|
*
|
|
|
|
* At most one entry for a given virtual address is permitted. Only a
|
|
|
|
* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
|
|
|
|
* used by tlb_flush_page.
|
|
|
|
*/
|
2015-04-26 18:49:24 +03:00
|
|
|
void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
|
|
|
|
hwaddr paddr, MemTxAttrs attrs,
|
|
|
|
int prot, int mmu_idx, target_ulong size);
|
2016-01-21 17:15:04 +03:00
|
|
|
/* tlb_set_page:
|
|
|
|
*
|
|
|
|
* This function is equivalent to calling tlb_set_page_with_attrs()
|
|
|
|
* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
|
|
|
|
* as a convenience for CPUs which don't use memory transaction attributes.
|
|
|
|
*/
|
|
|
|
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
|
|
|
|
hwaddr paddr, int prot,
|
|
|
|
int mmu_idx, target_ulong size);
|
2012-04-09 20:50:52 +04:00
|
|
|
#else
|
2018-10-09 20:45:54 +03:00
|
|
|
static inline void tlb_init(CPUState *cpu)
|
|
|
|
{
|
|
|
|
}
|
2020-06-12 22:02:26 +03:00
|
|
|
static inline void tlb_destroy(CPUState *cpu)
|
|
|
|
{
|
|
|
|
}
|
2013-09-04 03:29:02 +04:00
|
|
|
static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
|
2012-04-09 20:50:52 +04:00
|
|
|
{
|
|
|
|
}
|
2017-02-23 21:29:22 +03:00
|
|
|
static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
|
|
|
|
target_ulong addr)
|
|
|
|
{
|
|
|
|
}
|
2016-11-14 17:17:28 +03:00
|
|
|
static inline void tlb_flush(CPUState *cpu)
|
2012-04-09 20:50:52 +04:00
|
|
|
{
|
|
|
|
}
|
2017-02-23 21:29:22 +03:00
|
|
|
static inline void tlb_flush_all_cpus(CPUState *src_cpu)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
|
|
|
|
{
|
|
|
|
}
|
2015-08-25 17:45:09 +03:00
|
|
|
static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
|
2017-02-23 21:29:19 +03:00
|
|
|
target_ulong addr, uint16_t idxmap)
|
2015-08-25 17:45:09 +03:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2017-02-23 21:29:19 +03:00
|
|
|
static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
|
2015-08-25 17:45:09 +03:00
|
|
|
{
|
|
|
|
}
|
2017-02-23 21:29:22 +03:00
|
|
|
static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
|
|
|
|
target_ulong addr,
|
|
|
|
uint16_t idxmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
|
|
|
target_ulong addr,
|
|
|
|
uint16_t idxmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
|
|
|
|
{
|
|
|
|
}
|
2018-05-30 12:58:36 +03:00
|
|
|
|
2017-02-23 21:29:22 +03:00
|
|
|
static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
|
|
|
|
uint16_t idxmap)
|
|
|
|
{
|
|
|
|
}
|
2020-10-17 00:07:53 +03:00
|
|
|
static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
|
|
|
|
target_ulong addr,
|
|
|
|
uint16_t idxmap,
|
|
|
|
unsigned bits)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
|
|
|
|
target_ulong addr,
|
|
|
|
uint16_t idxmap,
|
|
|
|
unsigned bits)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void
|
|
|
|
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
|
|
|
|
uint16_t idxmap, unsigned bits)
|
|
|
|
{
|
|
|
|
}
|
2010-03-01 06:31:14 +03:00
|
|
|
#endif
|
2020-05-08 18:43:43 +03:00
|
|
|
/**
|
|
|
|
* probe_access:
|
|
|
|
* @env: CPUArchState
|
|
|
|
* @addr: guest virtual address to look up
|
|
|
|
* @size: size of the access
|
|
|
|
* @access_type: read, write or execute permission
|
|
|
|
* @mmu_idx: MMU index to use for lookup
|
|
|
|
* @retaddr: return address for unwinding
|
|
|
|
*
|
|
|
|
* Look up the guest virtual address @addr. Raise an exception if the
|
|
|
|
* page does not satisfy @access_type. Raise an exception if the
|
|
|
|
* access (@addr, @size) hits a watchpoint. For writes, mark a clean
|
|
|
|
* page as dirty.
|
|
|
|
*
|
|
|
|
* Finally, return the host address for a page that is backed by RAM,
|
|
|
|
* or NULL if the page requires I/O.
|
|
|
|
*/
|
2019-08-30 13:09:59 +03:00
|
|
|
void *probe_access(CPUArchState *env, target_ulong addr, int size,
|
|
|
|
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
|
|
|
|
|
|
|
|
static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
|
|
|
|
int mmu_idx, uintptr_t retaddr)
|
|
|
|
{
|
|
|
|
return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
|
|
|
|
}
|
2003-05-25 20:46:15 +04:00
|
|
|
|
2019-11-21 03:08:40 +03:00
|
|
|
static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
|
|
|
|
int mmu_idx, uintptr_t retaddr)
|
|
|
|
{
|
|
|
|
return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
|
|
|
|
}
|
|
|
|
|
2020-05-08 18:43:45 +03:00
|
|
|
/**
|
|
|
|
* probe_access_flags:
|
|
|
|
* @env: CPUArchState
|
|
|
|
* @addr: guest virtual address to look up
|
|
|
|
* @access_type: read, write or execute permission
|
|
|
|
* @mmu_idx: MMU index to use for lookup
|
|
|
|
* @nonfault: suppress the fault
|
|
|
|
* @phost: return value for host address
|
|
|
|
* @retaddr: return address for unwinding
|
|
|
|
*
|
|
|
|
* Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
|
|
|
|
* the page, and storing the host address for RAM in @phost.
|
|
|
|
*
|
|
|
|
* If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
|
|
|
|
* Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
|
|
|
|
* Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
|
|
|
|
* For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
|
|
|
|
*/
|
|
|
|
int probe_access_flags(CPUArchState *env, target_ulong addr,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
bool nonfault, void **phost, uintptr_t retaddr);
|
|
|
|
|
2003-05-25 20:46:15 +04:00
|
|
|
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
|
|
|
|
|
2015-09-26 19:23:42 +03:00
|
|
|
/* Estimated block size for TB allocation. */
|
|
|
|
/* ??? The following is based on a 2015 survey of x86_64 host output.
|
|
|
|
Better would seem to be some sort of dynamically sized TB array,
|
|
|
|
adapting to the block sizes actually being produced. */
|
2004-01-04 21:03:10 +03:00
|
|
|
#if defined(CONFIG_SOFTMMU)
|
2015-09-26 19:23:42 +03:00
|
|
|
#define CODE_GEN_AVG_BLOCK_SIZE 400
|
2004-01-04 21:03:10 +03:00
|
|
|
#else
|
2015-09-26 19:23:42 +03:00
|
|
|
#define CODE_GEN_AVG_BLOCK_SIZE 150
|
2004-01-04 21:03:10 +03:00
|
|
|
#endif
|
|
|
|
|
2017-07-12 07:08:21 +03:00
|
|
|
/*
|
|
|
|
* Translation Cache-related fields of a TB.
|
translate-all: use a binary search tree to track TBs in TBContext
This is a prerequisite for supporting multiple TCG contexts, since
we will have threads generating code in separate regions of
code_gen_buffer.
For this we need a new field (.size) in struct tb_tc to keep
track of the size of the translated code. This field uses a size_t
to avoid adding a hole to the struct, although really an unsigned
int would have been enough.
The comparison function we use is optimized for the common case:
insertions. Profiling shows that upon booting debian-arm, 98%
of comparisons are between existing tb's (i.e. a->size and b->size
are both !0), which happens during insertions (and removals, but
those are rare). The remaining cases are lookups. From reading the glib
sources we see that the first key is always the lookup key. However,
the code does not assume this to always be the case because this
behaviour is not guaranteed in the glib docs. However, we embed
this knowledge in the code as a branch hint for the compiler.
Note that tb_free does not free space in the code_gen_buffer anymore,
since we cannot easily know whether the tb is the last one inserted
in code_gen_buffer. The next patch in this series renames tb_free
to tb_remove to reflect this.
Performance-wise, lookups in tb_find_pc are the same as before:
O(log n). However, insertions are O(log n) instead of O(1), which
results in a small slowdown when booting debian-arm:
Performance counter stats for 'build/arm-softmmu/qemu-system-arm \
-machine type=virt -nographic -smp 1 -m 4096 \
-netdev user,id=unet,hostfwd=tcp::2222-:22 \
-device virtio-net-device,netdev=unet \
-drive file=img/arm/jessie-arm32.qcow2,id=myblock,index=0,if=none \
-device virtio-blk-device,drive=myblock \
-kernel img/arm/aarch32-current-linux-kernel-only.img \
-append console=ttyAMA0 root=/dev/vda1 \
-name arm,debug-threads=on -smp 1' (10 runs):
- Before:
8048.598422 task-clock (msec) # 0.931 CPUs utilized ( +- 0.28% )
16,974 context-switches # 0.002 M/sec ( +- 0.12% )
0 cpu-migrations # 0.000 K/sec
10,125 page-faults # 0.001 M/sec ( +- 1.23% )
35,144,901,879 cycles # 4.367 GHz ( +- 0.14% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,758,252,643 instructions # 1.87 insns per cycle ( +- 0.33% )
10,871,298,668 branches # 1350.707 M/sec ( +- 0.41% )
192,322,212 branch-misses # 1.77% of all branches ( +- 0.32% )
8.640869419 seconds time elapsed ( +- 0.57% )
- After:
8146.242027 task-clock (msec) # 0.923 CPUs utilized ( +- 1.23% )
17,016 context-switches # 0.002 M/sec ( +- 0.40% )
0 cpu-migrations # 0.000 K/sec
18,769 page-faults # 0.002 M/sec ( +- 0.45% )
35,660,956,120 cycles # 4.378 GHz ( +- 1.22% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,095,366,607 instructions # 1.83 insns per cycle ( +- 1.73% )
10,803,480,261 branches # 1326.192 M/sec ( +- 1.95% )
195,601,289 branch-misses # 1.81% of all branches ( +- 0.39% )
8.828660235 seconds time elapsed ( +- 0.38% )
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-06-24 02:00:11 +03:00
|
|
|
* This struct exists just for convenience; we keep track of TB's in a binary
|
|
|
|
* search tree, and the only fields needed to compare TB's in the tree are
|
|
|
|
* @ptr and @size.
|
|
|
|
* Note: the address of search data can be obtained by adding @size to @ptr.
|
2017-07-12 07:08:21 +03:00
|
|
|
*/
|
|
|
|
struct tb_tc {
|
|
|
|
void *ptr; /* pointer to the translated code */
|
translate-all: use a binary search tree to track TBs in TBContext
This is a prerequisite for supporting multiple TCG contexts, since
we will have threads generating code in separate regions of
code_gen_buffer.
For this we need a new field (.size) in struct tb_tc to keep
track of the size of the translated code. This field uses a size_t
to avoid adding a hole to the struct, although really an unsigned
int would have been enough.
The comparison function we use is optimized for the common case:
insertions. Profiling shows that upon booting debian-arm, 98%
of comparisons are between existing tb's (i.e. a->size and b->size
are both !0), which happens during insertions (and removals, but
those are rare). The remaining cases are lookups. From reading the glib
sources we see that the first key is always the lookup key. However,
the code does not assume this to always be the case because this
behaviour is not guaranteed in the glib docs. However, we embed
this knowledge in the code as a branch hint for the compiler.
Note that tb_free does not free space in the code_gen_buffer anymore,
since we cannot easily know whether the tb is the last one inserted
in code_gen_buffer. The next patch in this series renames tb_free
to tb_remove to reflect this.
Performance-wise, lookups in tb_find_pc are the same as before:
O(log n). However, insertions are O(log n) instead of O(1), which
results in a small slowdown when booting debian-arm:
Performance counter stats for 'build/arm-softmmu/qemu-system-arm \
-machine type=virt -nographic -smp 1 -m 4096 \
-netdev user,id=unet,hostfwd=tcp::2222-:22 \
-device virtio-net-device,netdev=unet \
-drive file=img/arm/jessie-arm32.qcow2,id=myblock,index=0,if=none \
-device virtio-blk-device,drive=myblock \
-kernel img/arm/aarch32-current-linux-kernel-only.img \
-append console=ttyAMA0 root=/dev/vda1 \
-name arm,debug-threads=on -smp 1' (10 runs):
- Before:
8048.598422 task-clock (msec) # 0.931 CPUs utilized ( +- 0.28% )
16,974 context-switches # 0.002 M/sec ( +- 0.12% )
0 cpu-migrations # 0.000 K/sec
10,125 page-faults # 0.001 M/sec ( +- 1.23% )
35,144,901,879 cycles # 4.367 GHz ( +- 0.14% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,758,252,643 instructions # 1.87 insns per cycle ( +- 0.33% )
10,871,298,668 branches # 1350.707 M/sec ( +- 0.41% )
192,322,212 branch-misses # 1.77% of all branches ( +- 0.32% )
8.640869419 seconds time elapsed ( +- 0.57% )
- After:
8146.242027 task-clock (msec) # 0.923 CPUs utilized ( +- 1.23% )
17,016 context-switches # 0.002 M/sec ( +- 0.40% )
0 cpu-migrations # 0.000 K/sec
18,769 page-faults # 0.002 M/sec ( +- 0.45% )
35,660,956,120 cycles # 4.378 GHz ( +- 1.22% )
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
65,095,366,607 instructions # 1.83 insns per cycle ( +- 1.73% )
10,803,480,261 branches # 1326.192 M/sec ( +- 1.95% )
195,601,289 branch-misses # 1.81% of all branches ( +- 0.39% )
8.828660235 seconds time elapsed ( +- 0.38% )
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-06-24 02:00:11 +03:00
|
|
|
size_t size;
|
2017-07-12 07:08:21 +03:00
|
|
|
};
|
|
|
|
|
2008-06-29 05:03:05 +04:00
|
|
|
struct TranslationBlock {
|
2004-04-26 01:28:44 +04:00
|
|
|
target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
|
|
|
target_ulong cs_base; /* CS base for this block */
|
2016-04-07 20:19:22 +03:00
|
|
|
uint32_t flags; /* flags defining in which context the code was generated */
|
2003-05-25 20:46:15 +04:00
|
|
|
uint16_t size; /* size of target code for this block (1 <=
|
|
|
|
size <= TARGET_PAGE_SIZE) */
|
2014-11-26 13:39:53 +03:00
|
|
|
uint16_t icount;
|
|
|
|
uint32_t cflags; /* compile flags */
|
2017-10-13 22:22:28 +03:00
|
|
|
#define CF_COUNT_MASK 0x00007fff
|
|
|
|
#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
|
|
|
|
#define CF_NOCACHE 0x00010000 /* To be freed after execution */
|
|
|
|
#define CF_USE_ICOUNT 0x00020000
|
translate-all: protect TB jumps with a per-destination-TB lock
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the destination TB (and therefore its jmp_lock)
from the origin TB, we introduce tb->jmp_dest[].
I considered not using a linked list of jumps, which simplifies
code and makes the struct smaller. However, it unnecessarily increases
memory usage, which results in a performance decrease. See for
instance these numbers booting+shutting down debian-arm:
Time (s) Rel. err (%) Abs. err (s) Rel. slowdown (%)
------------------------------------------------------------------------------
before 20.88 0.74 0.154512 0.
after 20.81 0.38 0.079078 -0.33524904
GTree 21.02 0.28 0.058856 0.67049808
GHashTable + xxhash 21.63 1.08 0.233604 3.5919540
Using a hash table or a binary tree to keep track of the jumps
doesn't really pay off, not only due to the increased memory usage,
but also because most TBs have only 0 or 1 jumps to them. The maximum
number of jumps when booting debian-arm that I measured is 35, but
as we can see in the histogram below a TB with that many incoming jumps
is extremely rare; the average TB has 0.80 incoming jumps.
n_jumps: 379208; avg jumps/tb: 0.801099
dist: [0.0,1.0)|▄█▁▁▁▁▁▁▁▁▁▁▁ ▁▁▁▁▁▁ ▁▁▁ ▁▁▁ ▁|[34.0,35.0]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03 03:34:06 +03:00
|
|
|
#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
|
2017-10-13 22:22:28 +03:00
|
|
|
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
|
2019-01-29 14:46:06 +03:00
|
|
|
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
|
|
|
|
#define CF_CLUSTER_SHIFT 24
|
2017-07-11 21:29:37 +03:00
|
|
|
/* cflags' mask for hashing/comparison */
|
2017-10-13 22:15:06 +03:00
|
|
|
#define CF_HASH_MASK \
|
2019-01-29 14:46:06 +03:00
|
|
|
(CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER_MASK)
|
2004-02-17 01:11:32 +03:00
|
|
|
|
2017-07-04 11:42:32 +03:00
|
|
|
/* Per-vCPU dynamic tracing state used to generate this TB */
|
|
|
|
uint32_t trace_vcpu_dstate;
|
|
|
|
|
2017-07-12 07:08:21 +03:00
|
|
|
struct tb_tc tc;
|
|
|
|
|
2015-06-30 12:35:09 +03:00
|
|
|
/* original tb when cflags has CF_NOCACHE */
|
|
|
|
struct TranslationBlock *orig_tb;
|
2004-01-04 21:03:10 +03:00
|
|
|
/* first and second physical page containing code. The lower bit
|
2017-07-27 03:22:51 +03:00
|
|
|
of the pointer tells the index in page_next[].
|
|
|
|
The list is protected by the TB's page('s) lock(s) */
|
2017-08-04 01:37:15 +03:00
|
|
|
uintptr_t page_next[2];
|
2010-03-12 19:54:58 +03:00
|
|
|
tb_page_addr_t page_addr[2];
|
2004-01-04 21:03:10 +03:00
|
|
|
|
translate-all: protect TB jumps with a per-destination-TB lock
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the destination TB (and therefore its jmp_lock)
from the origin TB, we introduce tb->jmp_dest[].
I considered not using a linked list of jumps, which simplifies
code and makes the struct smaller. However, it unnecessarily increases
memory usage, which results in a performance decrease. See for
instance these numbers booting+shutting down debian-arm:
Time (s) Rel. err (%) Abs. err (s) Rel. slowdown (%)
------------------------------------------------------------------------------
before 20.88 0.74 0.154512 0.
after 20.81 0.38 0.079078 -0.33524904
GTree 21.02 0.28 0.058856 0.67049808
GHashTable + xxhash 21.63 1.08 0.233604 3.5919540
Using a hash table or a binary tree to keep track of the jumps
doesn't really pay off, not only due to the increased memory usage,
but also because most TBs have only 0 or 1 jumps to them. The maximum
number of jumps when booting debian-arm that I measured is 35, but
as we can see in the histogram below a TB with that many incoming jumps
is extremely rare; the average TB has 0.80 incoming jumps.
n_jumps: 379208; avg jumps/tb: 0.801099
dist: [0.0,1.0)|▄█▁▁▁▁▁▁▁▁▁▁▁ ▁▁▁▁▁▁ ▁▁▁ ▁▁▁ ▁|[34.0,35.0]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03 03:34:06 +03:00
|
|
|
/* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
|
|
|
|
QemuSpin jmp_lock;
|
|
|
|
|
2016-04-10 23:35:45 +03:00
|
|
|
/* The following data are used to directly call another TB from
|
|
|
|
* the code of this one. This can be done either by emitting direct or
|
|
|
|
* indirect native jump instructions. These jumps are reset so that the TB
|
2017-06-24 02:43:01 +03:00
|
|
|
* just continues its execution. The TB can be linked to another one by
|
2016-04-10 23:35:45 +03:00
|
|
|
* setting one of the jump targets (or patching the jump instruction). Only
|
|
|
|
* two of such jumps are supported.
|
|
|
|
*/
|
|
|
|
uint16_t jmp_reset_offset[2]; /* offset of original jump target */
|
|
|
|
#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
|
2017-08-01 08:02:31 +03:00
|
|
|
uintptr_t jmp_target_arg[2]; /* target address or offset */
|
|
|
|
|
translate-all: protect TB jumps with a per-destination-TB lock
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the destination TB (and therefore its jmp_lock)
from the origin TB, we introduce tb->jmp_dest[].
I considered not using a linked list of jumps, which simplifies
code and makes the struct smaller. However, it unnecessarily increases
memory usage, which results in a performance decrease. See for
instance these numbers booting+shutting down debian-arm:
Time (s) Rel. err (%) Abs. err (s) Rel. slowdown (%)
------------------------------------------------------------------------------
before 20.88 0.74 0.154512 0.
after 20.81 0.38 0.079078 -0.33524904
GTree 21.02 0.28 0.058856 0.67049808
GHashTable + xxhash 21.63 1.08 0.233604 3.5919540
Using a hash table or a binary tree to keep track of the jumps
doesn't really pay off, not only due to the increased memory usage,
but also because most TBs have only 0 or 1 jumps to them. The maximum
number of jumps when booting debian-arm that I measured is 35, but
as we can see in the histogram below a TB with that many incoming jumps
is extremely rare; the average TB has 0.80 incoming jumps.
n_jumps: 379208; avg jumps/tb: 0.801099
dist: [0.0,1.0)|▄█▁▁▁▁▁▁▁▁▁▁▁ ▁▁▁▁▁▁ ▁▁▁ ▁▁▁ ▁|[34.0,35.0]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03 03:34:06 +03:00
|
|
|
/*
|
|
|
|
* Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
|
|
|
|
* Each TB can have two outgoing jumps, and therefore can participate
|
|
|
|
* in two lists. The list entries are kept in jmp_list_next[2]. The least
|
|
|
|
* significant bit (LSB) of the pointers in these lists is used to encode
|
|
|
|
* which of the two list entries is to be used in the pointed TB.
|
|
|
|
*
|
|
|
|
* List traversals are protected by jmp_lock. The destination TB of each
|
|
|
|
* outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
|
|
|
|
* can be acquired from any origin TB.
|
|
|
|
*
|
|
|
|
* jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
|
|
|
|
* being invalidated, so that no further outgoing jumps from it can be set.
|
|
|
|
*
|
|
|
|
* jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
|
|
|
|
* to a destination TB that has CF_INVALID set.
|
2016-04-10 23:35:45 +03:00
|
|
|
*/
|
translate-all: protect TB jumps with a per-destination-TB lock
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the destination TB (and therefore its jmp_lock)
from the origin TB, we introduce tb->jmp_dest[].
I considered not using a linked list of jumps, which simplifies
code and makes the struct smaller. However, it unnecessarily increases
memory usage, which results in a performance decrease. See for
instance these numbers booting+shutting down debian-arm:
Time (s) Rel. err (%) Abs. err (s) Rel. slowdown (%)
------------------------------------------------------------------------------
before 20.88 0.74 0.154512 0.
after 20.81 0.38 0.079078 -0.33524904
GTree 21.02 0.28 0.058856 0.67049808
GHashTable + xxhash 21.63 1.08 0.233604 3.5919540
Using a hash table or a binary tree to keep track of the jumps
doesn't really pay off, not only due to the increased memory usage,
but also because most TBs have only 0 or 1 jumps to them. The maximum
number of jumps when booting debian-arm that I measured is 35, but
as we can see in the histogram below a TB with that many incoming jumps
is extremely rare; the average TB has 0.80 incoming jumps.
n_jumps: 379208; avg jumps/tb: 0.801099
dist: [0.0,1.0)|▄█▁▁▁▁▁▁▁▁▁▁▁ ▁▁▁▁▁▁ ▁▁▁ ▁▁▁ ▁|[34.0,35.0]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03 03:34:06 +03:00
|
|
|
uintptr_t jmp_list_head;
|
2016-03-21 23:11:00 +03:00
|
|
|
uintptr_t jmp_list_next[2];
|
translate-all: protect TB jumps with a per-destination-TB lock
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the destination TB (and therefore its jmp_lock)
from the origin TB, we introduce tb->jmp_dest[].
I considered not using a linked list of jumps, which simplifies
code and makes the struct smaller. However, it unnecessarily increases
memory usage, which results in a performance decrease. See for
instance these numbers booting+shutting down debian-arm:
Time (s) Rel. err (%) Abs. err (s) Rel. slowdown (%)
------------------------------------------------------------------------------
before 20.88 0.74 0.154512 0.
after 20.81 0.38 0.079078 -0.33524904
GTree 21.02 0.28 0.058856 0.67049808
GHashTable + xxhash 21.63 1.08 0.233604 3.5919540
Using a hash table or a binary tree to keep track of the jumps
doesn't really pay off, not only due to the increased memory usage,
but also because most TBs have only 0 or 1 jumps to them. The maximum
number of jumps when booting debian-arm that I measured is 35, but
as we can see in the histogram below a TB with that many incoming jumps
is extremely rare; the average TB has 0.80 incoming jumps.
n_jumps: 379208; avg jumps/tb: 0.801099
dist: [0.0,1.0)|▄█▁▁▁▁▁▁▁▁▁▁▁ ▁▁▁▁▁▁ ▁▁▁ ▁▁▁ ▁|[34.0,35.0]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03 03:34:06 +03:00
|
|
|
uintptr_t jmp_dest[2];
|
2008-06-29 05:03:05 +04:00
|
|
|
};
|
2003-05-25 20:46:15 +04:00
|
|
|
|
2017-07-11 21:29:37 +03:00
|
|
|
extern bool parallel_cpus;
|
|
|
|
|
2020-09-23 13:56:46 +03:00
|
|
|
/* Hide the qatomic_read to make code a little easier on the eyes */
|
2017-07-11 21:29:37 +03:00
|
|
|
static inline uint32_t tb_cflags(const TranslationBlock *tb)
|
|
|
|
{
|
2020-09-23 13:56:46 +03:00
|
|
|
return qatomic_read(&tb->cflags);
|
2017-07-11 21:29:37 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* current cflags for hashing/comparison */
|
|
|
|
static inline uint32_t curr_cflags(void)
|
|
|
|
{
|
2017-10-13 22:22:28 +03:00
|
|
|
return (parallel_cpus ? CF_PARALLEL : 0)
|
2020-08-19 14:17:19 +03:00
|
|
|
| (icount_enabled() ? CF_USE_ICOUNT : 0);
|
2017-07-11 21:29:37 +03:00
|
|
|
}
|
|
|
|
|
2018-06-29 23:07:10 +03:00
|
|
|
/* TranslationBlock invalidate API */
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2018-07-02 15:45:25 +03:00
|
|
|
void tb_invalidate_phys_addr(target_ulong addr);
|
2018-06-29 23:07:10 +03:00
|
|
|
void tb_invalidate_phys_range(target_ulong start, target_ulong end);
|
2018-07-02 15:45:25 +03:00
|
|
|
#else
|
|
|
|
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
|
2018-06-29 23:07:10 +03:00
|
|
|
#endif
|
2015-06-24 05:31:15 +03:00
|
|
|
void tb_flush(CPUState *cpu);
|
2010-03-12 19:54:58 +03:00
|
|
|
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
|
2017-04-27 06:29:14 +03:00
|
|
|
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
|
2017-07-11 21:29:37 +03:00
|
|
|
target_ulong cs_base, uint32_t flags,
|
|
|
|
uint32_t cf_mask);
|
2017-08-01 08:02:31 +03:00
|
|
|
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
|
2003-05-25 20:46:15 +04:00
|
|
|
|
2016-07-26 03:39:16 +03:00
|
|
|
/* GETPC is the true target of the return instruction that we'll execute. */
|
2011-10-05 22:03:02 +04:00
|
|
|
#if defined(CONFIG_TCG_INTERPRETER)
|
2012-04-17 21:22:39 +04:00
|
|
|
extern uintptr_t tci_tb_ptr;
|
2016-07-26 03:39:16 +03:00
|
|
|
# define GETPC() tci_tb_ptr
|
2013-08-27 21:22:54 +04:00
|
|
|
#else
|
2016-07-26 03:39:16 +03:00
|
|
|
# define GETPC() \
|
2013-08-27 21:22:54 +04:00
|
|
|
((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* The true return address will often point to a host insn that is part of
|
|
|
|
the next translated guest insn. Adjust the address backward to point to
|
|
|
|
the middle of the call insn. Subtracting one would do the job except for
|
|
|
|
several compressed mode architectures (arm, mips) which set the low bit
|
|
|
|
to indicate the compressed mode; subtracting two works around that. It
|
|
|
|
is also the case that there are no host isas that contain a call insn
|
|
|
|
smaller than 4 bytes, so we don't worry about special-casing this. */
|
2015-08-18 06:28:18 +03:00
|
|
|
#define GETPC_ADJ 2
|
2011-09-21 22:13:16 +04:00
|
|
|
|
2018-02-23 04:50:29 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG)
|
|
|
|
void assert_no_pages_locked(void);
|
|
|
|
#else
|
|
|
|
static inline void assert_no_pages_locked(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2004-10-01 02:22:08 +04:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2003-10-28 00:24:54 +03:00
|
|
|
|
2018-06-15 16:57:14 +03:00
|
|
|
/**
|
|
|
|
* iotlb_to_section:
|
|
|
|
* @cpu: CPU performing the access
|
|
|
|
* @index: TCG CPU IOTLB entry
|
|
|
|
*
|
|
|
|
* Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
|
|
|
|
* it refers to. @index will have been initially created and returned
|
|
|
|
* by memory_region_section_get_iotlb().
|
|
|
|
*/
|
|
|
|
struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
|
|
|
|
hwaddr index, MemTxAttrs attrs);
|
2003-10-28 00:24:54 +03:00
|
|
|
#endif
|
2004-01-04 21:03:10 +03:00
|
|
|
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2015-08-11 11:57:52 +03:00
|
|
|
void mmap_lock(void);
|
|
|
|
void mmap_unlock(void);
|
2016-10-27 18:10:00 +03:00
|
|
|
bool have_mmap_lock(void);
|
2015-08-11 11:57:52 +03:00
|
|
|
|
2019-02-07 01:11:04 +03:00
|
|
|
/**
|
|
|
|
* get_page_addr_code() - user-mode version
|
|
|
|
* @env: CPUArchState
|
|
|
|
* @addr: guest virtual address of guest code
|
|
|
|
*
|
|
|
|
* Returns @addr.
|
|
|
|
*/
|
|
|
|
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
|
|
|
|
target_ulong addr)
|
2004-01-04 21:03:10 +03:00
|
|
|
{
|
|
|
|
return addr;
|
|
|
|
}
|
2018-11-04 00:40:22 +03:00
|
|
|
|
|
|
|
/**
|
|
|
|
* get_page_addr_code_hostp() - user-mode version
|
|
|
|
* @env: CPUArchState
|
|
|
|
* @addr: guest virtual address of guest code
|
|
|
|
*
|
|
|
|
* Returns @addr.
|
|
|
|
*
|
|
|
|
* If @hostp is non-NULL, sets *@hostp to the host address where @addr's content
|
|
|
|
* is kept.
|
|
|
|
*/
|
|
|
|
static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
|
|
|
|
target_ulong addr,
|
|
|
|
void **hostp)
|
|
|
|
{
|
|
|
|
if (hostp) {
|
|
|
|
*hostp = g2h(addr);
|
|
|
|
}
|
|
|
|
return addr;
|
|
|
|
}
|
2004-01-04 21:03:10 +03:00
|
|
|
#else
|
2015-08-11 11:57:52 +03:00
|
|
|
static inline void mmap_lock(void) {}
|
|
|
|
static inline void mmap_unlock(void) {}
|
|
|
|
|
2019-02-07 01:11:04 +03:00
|
|
|
/**
|
|
|
|
* get_page_addr_code() - full-system version
|
|
|
|
* @env: CPUArchState
|
|
|
|
* @addr: guest virtual address of guest code
|
|
|
|
*
|
|
|
|
* If we cannot translate and execute from the entire RAM page, or if
|
|
|
|
* the region is not backed by RAM, returns -1. Otherwise, returns the
|
|
|
|
* ram_addr_t corresponding to the guest code at @addr.
|
|
|
|
*
|
|
|
|
* Note: this function can trigger an exception.
|
|
|
|
*/
|
|
|
|
tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr);
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2015-09-11 08:39:43 +03:00
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2018-11-04 00:40:22 +03:00
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/**
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* get_page_addr_code_hostp() - full-system version
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* @env: CPUArchState
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* @addr: guest virtual address of guest code
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*
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* See get_page_addr_code() (full-system version) for documentation on the
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* return value.
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*
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* Sets *@hostp (when @hostp is non-NULL) as follows.
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* If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
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* to the host address where @addr's content is kept.
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*
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* Note: this function can trigger an exception.
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*/
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tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
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void **hostp);
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2015-09-11 08:39:43 +03:00
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
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/* exec.c */
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void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
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MemoryRegionSection *
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2016-01-21 17:15:05 +03:00
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address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
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2018-06-15 16:57:16 +03:00
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hwaddr *xlat, hwaddr *plen,
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MemTxAttrs attrs, int *prot);
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2015-09-11 08:39:43 +03:00
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hwaddr memory_region_section_get_iotlb(CPUState *cpu,
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2019-09-20 07:09:58 +03:00
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MemoryRegionSection *section);
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2004-01-04 21:03:10 +03:00
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#endif
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2005-02-11 01:05:51 +03:00
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2009-04-06 00:08:59 +04:00
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/* vl.c */
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extern int singlestep;
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2008-10-23 17:52:00 +04:00
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#endif
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