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qemu/target/sparc/cpu-feature.h.inc

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target/sparc: Define features via cpu-feature.h.inc Manage feature bits automatically. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-16 03:02:33 +03:00
FEATURE(FLOAT128)
FEATURE(MUL)
FEATURE(DIV)
FEATURE(VIS1)
FEATURE(VIS2)
FEATURE(FSMULD)
FEATURE(HYPV)
FEATURE(CMT)
FEATURE(GL)
FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */
FEATURE(ASR17)
FEATURE(CACHE_CTRL)
FEATURE(POWERDOWN)
FEATURE(CASA)
target/sparc: Implement FMAf extension Rearrange PDIST so that do_dddd is general purpose and may be re-used for FMADDd etc. Add pickNaN and pickNaNMulAdd. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-04 22:13:00 +03:00
FEATURE(FMAF)
target/sparc: Add feature bits for VIS 3 The manual separates VIS 3 and VIS 3B, even though they are both present in all extant cpus. For clarity, let the translator match the manual but otherwise leave them on the same feature bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-04 22:21:37 +03:00
FEATURE(VIS3)
target/sparc: Implement IMA extension Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05 05:40:36 +03:00
FEATURE(IMA)
target/sparc: Add feature bit for VIS4 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05 05:44:28 +03:00
FEATURE(VIS4)
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