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qemu/target/loongarch/insns.decode

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target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
# SPDX-License-Identifier: GPL-2.0-or-later
#
# LoongArch instruction decode definitions.
#
# Copyright (c) 2021 Loongson Technology Corporation Limited
#
#
# Fields
#
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
%i14s2 10:s14 !function=shl_2
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
%sa2p1 15:2 !function=plus_1
target/loongarch: Add branch instruction translation This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:05 +03:00
%offs21 0:s5 10:16 !function=shl_2
%offs16 10:s16 !function=shl_2
%offs26 0:s10 10:16 !function=shl_2
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
#
# Argument sets
#
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
&i imm
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
&r_i rd imm
target/loongarch: Add fixed point bit instruction translation This includes: - EXT.W.{B/H} - CL{O/Z}.{W/D}, CT{O/Z}.{W/D} - BYTEPICK.{W/D} - REVB.{2H/4H/2W/D} - REVH.{2W/D} - BITREV.{4B/8B}, BITREV.{W/D} - BSTRINS.{W/D}, BSTRPICK.{W/D} - MASKEQZ, MASKNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:56 +03:00
&rr rd rj
target/loongarch: Add fixed point extra instruction translation This includes: - CRC[C].W.{B/H/W/D}.W - SYSCALL - BREAK - ASRT{LE/GT}.D - RDTIME{L/H}.W, RDTIME.D - CPUCFG Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:59 +03:00
&rr_jk rj rk
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
&rrr rd rj rk
&rr_i rd rj imm
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
&hint_r_i hint rj imm
target/loongarch: Add preldx instruction Resolve the issue of starting the Loongnix 20.5[1] system failure. Logs: Loading Linux 4.19.0-19-loongson-3 ... Loading initial ramdisk ... PROGRESS CODE: V02010004 I0 PROGRESS CODE: V03101019 I0 Error: unknown opcode. 90000000003a3e6c: 0x382c6d82 [1] http://pkg.loongnix.cn/loongnix/isos/Loongnix-20.5/Loongnix-20.5.cartoon.gui.loongarch64.en.qcow2 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230905123910.3052023-1-gaosong@loongson.cn>
2023-09-05 15:39:10 +03:00
&hint_rr hint rj rk
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
&rrr_sa rd rj rk sa
target/loongarch: Add fixed point bit instruction translation This includes: - EXT.W.{B/H} - CL{O/Z}.{W/D}, CT{O/Z}.{W/D} - BYTEPICK.{W/D} - REVB.{2H/4H/2W/D} - REVH.{2W/D} - BITREV.{4B/8B}, BITREV.{W/D} - BSTRINS.{W/D}, BSTRPICK.{W/D} - MASKEQZ, MASKNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:56 +03:00
&rr_ms_ls rd rj ms ls
target/loongarch: Add floating point arithmetic instruction translation This includes: - F{ADD/SUB/MUL/DIV}.{S/D} - F{MADD/MSUB/NMADD/NMSUB}.{S/D} - F{MAX/MIN}.{S/D} - F{MAXA/MINA}.{S/D} - F{ABS/NEG}.{S/D} - F{SQRT/RECIP/RSQRT}.{S/D} - F{SCALEB/LOGB/COPYSIGN}.{S/D} - FCLASS.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-11-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:00 +03:00
&ff fd fj
&fff fd fj fk
&ffff fd fj fk fa
target/loongarch: Add floating point comparison instruction translation This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-12-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:01 +03:00
&cff_fcond cd fj fk fcond
target/loongarch: Add floating point move instruction translation This includes: - FMOV.{S/D} - FSEL - MOVGR2FR.{W/D}, MOVGR2FRH.W - MOVFR2GR.{S/D}, MOVFRH2GR.S - MOVGR2FCSR, MOVFCSR2GR - MOVFR2CF, MOVCF2FR - MOVGR2CF, MOVCF2GR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-14-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:03 +03:00
&fffc fd fj fk ca
&fr fd rj
&rf rd fj
&fcsrd_r fcsrd rj
&r_fcsrs rd fcsrs
&cf cd fj
&fc fd cj
&cr cd rj
&rc rd cj
target/loongarch: Add floating point load/store instruction translation This includes: - FLD.{S/D}, FST.{S/D} - FLDX.{S/D}, FSTX.{S/D} - FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-15-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:04 +03:00
&frr fd rj rk
&fr_i fd rj imm
target/loongarch: Add branch instruction translation This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:05 +03:00
&r_offs rj offs
&c_offs cj offs
&offs offs
&rr_offs rj rd offs
target/loongarch: Add LoongArch CSR instruction This includes: - CSRRD - CSRWR - CSRXCHG Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-26-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:15 +03:00
&r_csr rd csr
&rr_csr rd rj csr
target/loongarch: Add TLB instruction support This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-28-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:17 +03:00
&empty
&i_rr imm rj rk
target/loongarch: Add other core instructions support This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-29-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:18 +03:00
&cop_r_i cop rj imm
&j_i rj imm
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
#
# Formats
#
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
@i15 .... ........ ..... imm:15 &i
target/loongarch: Add fixed point bit instruction translation This includes: - EXT.W.{B/H} - CL{O/Z}.{W/D}, CT{O/Z}.{W/D} - BYTEPICK.{W/D} - REVB.{2H/4H/2W/D} - REVH.{2W/D} - BITREV.{4B/8B}, BITREV.{W/D} - BSTRINS.{W/D}, BSTRPICK.{W/D} - MASKEQZ, MASKNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:56 +03:00
@rr .... ........ ..... ..... rj:5 rd:5 &rr
target/loongarch: Add fixed point extra instruction translation This includes: - CRC[C].W.{B/H/W/D}.W - SYSCALL - BREAK - ASRT{LE/GT}.D - RDTIME{L/H}.W, RDTIME.D - CPUCFG Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:59 +03:00
@rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
@r_i20 .... ... imm:s20 rd:5 &r_i
target/loongarch: Add fixed point shift instruction translation This includes: - SLL.W, SRL.W, SRA.W, ROTR.W - SLLI.W, SRLI.W, SRAI.W, ROTRI.W - SLL.D, SRL.D, SRA.D, ROTR.D - SLLI.D, SRLI.D, SRAI.D, ROTRI.D Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
target/loongarch: Add other core instructions support This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-29-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:18 +03:00
@rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
target/loongarch: Disassemble jirl properly While jirl shares the same instruction format as bne etc, it is not assembled the same. In particular, rd is printed first not second and the immediate is not pc-relative. Decode into the arg_rr_i structure, which prints correctly. This changes the "offs" member to "imm", to update translate. Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-18 03:32:38 +03:00
@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
target/loongarch: Add preldx instruction Resolve the issue of starting the Loongnix 20.5[1] system failure. Logs: Loading Linux 4.19.0-19-loongson-3 ... Loading initial ramdisk ... PROGRESS CODE: V02010004 I0 PROGRESS CODE: V03101019 I0 Error: unknown opcode. 90000000003a3e6c: 0x382c6d82 [1] http://pkg.loongnix.cn/loongnix/isos/Loongnix-20.5/Loongnix-20.5.cartoon.gui.loongarch64.en.qcow2 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230905123910.3052023-1-gaosong@loongson.cn>
2023-09-05 15:39:10 +03:00
@hint_rr .... ........ ..... rk:5 rj:5 hint:5 &hint_rr
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
target/loongarch: Add fixed point bit instruction translation This includes: - EXT.W.{B/H} - CL{O/Z}.{W/D}, CT{O/Z}.{W/D} - BYTEPICK.{W/D} - REVB.{2H/4H/2W/D} - REVH.{2W/D} - BITREV.{4B/8B}, BITREV.{W/D} - BSTRINS.{W/D}, BSTRPICK.{W/D} - MASKEQZ, MASKNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:56 +03:00
@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
@rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls
@rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls
target/loongarch: Add floating point arithmetic instruction translation This includes: - F{ADD/SUB/MUL/DIV}.{S/D} - F{MADD/MSUB/NMADD/NMSUB}.{S/D} - F{MAX/MIN}.{S/D} - F{MAXA/MINA}.{S/D} - F{ABS/NEG}.{S/D} - F{SQRT/RECIP/RSQRT}.{S/D} - F{SCALEB/LOGB/COPYSIGN}.{S/D} - FCLASS.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-11-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:00 +03:00
@ff .... ........ ..... ..... fj:5 fd:5 &ff
@fff .... ........ ..... fk:5 fj:5 fd:5 &fff
@ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff
target/loongarch: Add floating point comparison instruction translation This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-12-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:01 +03:00
@cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond
target/loongarch: Add floating point move instruction translation This includes: - FMOV.{S/D} - FSEL - MOVGR2FR.{W/D}, MOVGR2FRH.W - MOVFR2GR.{S/D}, MOVFRH2GR.S - MOVGR2FCSR, MOVFCSR2GR - MOVFR2CF, MOVCF2FR - MOVGR2CF, MOVCF2GR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-14-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:03 +03:00
@fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc
@fr .... ........ ..... ..... rj:5 fd:5 &fr
@rf .... ........ ..... ..... fj:5 rd:5 &rf
@fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r
@r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs
@cf .... ........ ..... ..... fj:5 .. cd:3 &cf
@fc .... ........ ..... ..... .. cj:3 fd:5 &fc
@cr .... ........ ..... ..... rj:5 .. cd:3 &cr
@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
target/loongarch: Add floating point load/store instruction translation This includes: - FLD.{S/D}, FST.{S/D} - FLDX.{S/D}, FSTX.{S/D} - FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-15-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:04 +03:00
@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
target/loongarch: Add branch instruction translation This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:05 +03:00
@r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21
@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
@offs26 .... .. .......................... &offs offs=%offs26
@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
target/loongarch: Add LoongArch CSR instruction This includes: - CSRRD - CSRWR - CSRXCHG Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-26-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:15 +03:00
@r_csr .... .... csr:14 ..... rd:5 &r_csr
@rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
target/loongarch: Add TLB instruction support This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-28-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:17 +03:00
@empty .... ........ ..... ..... ..... ..... &empty
@i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr
target/loongarch: Add other core instructions support This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-29-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:18 +03:00
@cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i
@j_i .... ........ .. imm:8 rj:5 ..... &j_i
target/loongarch: Add fixed point arithmetic instruction translation This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
#
# Fixed point arithmetic operation instruction
#
add_w 0000 00000001 00000 ..... ..... ..... @rrr
add_d 0000 00000001 00001 ..... ..... ..... @rrr
sub_w 0000 00000001 00010 ..... ..... ..... @rrr
sub_d 0000 00000001 00011 ..... ..... ..... @rrr
slt 0000 00000001 00100 ..... ..... ..... @rrr
sltu 0000 00000001 00101 ..... ..... ..... @rrr
slti 0000 001000 ............ ..... ..... @rr_i12
sltui 0000 001001 ............ ..... ..... @rr_i12
nor 0000 00000001 01000 ..... ..... ..... @rrr
and 0000 00000001 01001 ..... ..... ..... @rrr
or 0000 00000001 01010 ..... ..... ..... @rrr
xor 0000 00000001 01011 ..... ..... ..... @rrr
orn 0000 00000001 01100 ..... ..... ..... @rrr
andn 0000 00000001 01101 ..... ..... ..... @rrr
mul_w 0000 00000001 11000 ..... ..... ..... @rrr
mulh_w 0000 00000001 11001 ..... ..... ..... @rrr
mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr
mul_d 0000 00000001 11011 ..... ..... ..... @rrr
mulh_d 0000 00000001 11100 ..... ..... ..... @rrr
mulh_du 0000 00000001 11101 ..... ..... ..... @rrr
mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr
mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr
div_w 0000 00000010 00000 ..... ..... ..... @rrr
mod_w 0000 00000010 00001 ..... ..... ..... @rrr
div_wu 0000 00000010 00010 ..... ..... ..... @rrr
mod_wu 0000 00000010 00011 ..... ..... ..... @rrr
div_d 0000 00000010 00100 ..... ..... ..... @rrr
mod_d 0000 00000010 00101 ..... ..... ..... @rrr
div_du 0000 00000010 00110 ..... ..... ..... @rrr
mod_du 0000 00000010 00111 ..... ..... ..... @rrr
alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1
alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1
alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1
lu12i_w 0001 010 .................... ..... @r_i20
lu32i_d 0001 011 .................... ..... @r_i20
lu52i_d 0000 001100 ............ ..... ..... @rr_i12
pcaddi 0001 100 .................... ..... @r_i20
pcalau12i 0001 101 .................... ..... @r_i20
pcaddu12i 0001 110 .................... ..... @r_i20
pcaddu18i 0001 111 .................... ..... @r_i20
addi_w 0000 001010 ............ ..... ..... @rr_i12
addi_d 0000 001011 ............ ..... ..... @rr_i12
addu16i_d 0001 00 ................ ..... ..... @rr_i16
andi 0000 001101 ............ ..... ..... @rr_ui12
ori 0000 001110 ............ ..... ..... @rr_ui12
xori 0000 001111 ............ ..... ..... @rr_ui12
target/loongarch: Add fixed point shift instruction translation This includes: - SLL.W, SRL.W, SRA.W, ROTR.W - SLLI.W, SRLI.W, SRAI.W, ROTRI.W - SLL.D, SRL.D, SRA.D, ROTR.D - SLLI.D, SRLI.D, SRAI.D, ROTRI.D Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:55 +03:00
#
# Fixed point shift operation instruction
#
sll_w 0000 00000001 01110 ..... ..... ..... @rrr
srl_w 0000 00000001 01111 ..... ..... ..... @rrr
sra_w 0000 00000001 10000 ..... ..... ..... @rrr
sll_d 0000 00000001 10001 ..... ..... ..... @rrr
srl_d 0000 00000001 10010 ..... ..... ..... @rrr
sra_d 0000 00000001 10011 ..... ..... ..... @rrr
rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6
target/loongarch: Add fixed point bit instruction translation This includes: - EXT.W.{B/H} - CL{O/Z}.{W/D}, CT{O/Z}.{W/D} - BYTEPICK.{W/D} - REVB.{2H/4H/2W/D} - REVH.{2W/D} - BITREV.{4B/8B}, BITREV.{W/D} - BSTRINS.{W/D}, BSTRPICK.{W/D} - MASKEQZ, MASKNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:56 +03:00
#
# Fixed point bit operation instruction
#
ext_w_h 0000 00000000 00000 10110 ..... ..... @rr
ext_w_b 0000 00000000 00000 10111 ..... ..... @rr
clo_w 0000 00000000 00000 00100 ..... ..... @rr
clz_w 0000 00000000 00000 00101 ..... ..... @rr
cto_w 0000 00000000 00000 00110 ..... ..... @rr
ctz_w 0000 00000000 00000 00111 ..... ..... @rr
clo_d 0000 00000000 00000 01000 ..... ..... @rr
clz_d 0000 00000000 00000 01001 ..... ..... @rr
cto_d 0000 00000000 00000 01010 ..... ..... @rr
ctz_d 0000 00000000 00000 01011 ..... ..... @rr
revb_2h 0000 00000000 00000 01100 ..... ..... @rr
revb_4h 0000 00000000 00000 01101 ..... ..... @rr
revb_2w 0000 00000000 00000 01110 ..... ..... @rr
revb_d 0000 00000000 00000 01111 ..... ..... @rr
revh_2w 0000 00000000 00000 10000 ..... ..... @rr
revh_d 0000 00000000 00000 10001 ..... ..... @rr
bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr
bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr
bitrev_w 0000 00000000 00000 10100 ..... ..... @rr
bitrev_d 0000 00000000 00000 10101 ..... ..... @rr
bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2
bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3
maskeqz 0000 00000001 00110 ..... ..... ..... @rrr
masknez 0000 00000001 00111 ..... ..... ..... @rrr
bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw
bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw
bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd
bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
#
# Fixed point load/store instruction
#
ld_b 0010 100000 ............ ..... ..... @rr_i12
ld_h 0010 100001 ............ ..... ..... @rr_i12
ld_w 0010 100010 ............ ..... ..... @rr_i12
ld_d 0010 100011 ............ ..... ..... @rr_i12
st_b 0010 100100 ............ ..... ..... @rr_i12
st_h 0010 100101 ............ ..... ..... @rr_i12
st_w 0010 100110 ............ ..... ..... @rr_i12
st_d 0010 100111 ............ ..... ..... @rr_i12
ld_bu 0010 101000 ............ ..... ..... @rr_i12
ld_hu 0010 101001 ............ ..... ..... @rr_i12
ld_wu 0010 101010 ............ ..... ..... @rr_i12
ldx_b 0011 10000000 00000 ..... ..... ..... @rrr
ldx_h 0011 10000000 01000 ..... ..... ..... @rrr
ldx_w 0011 10000000 10000 ..... ..... ..... @rrr
ldx_d 0011 10000000 11000 ..... ..... ..... @rrr
stx_b 0011 10000001 00000 ..... ..... ..... @rrr
stx_h 0011 10000001 01000 ..... ..... ..... @rrr
stx_w 0011 10000001 10000 ..... ..... ..... @rrr
stx_d 0011 10000001 11000 ..... ..... ..... @rrr
ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
preld 0010 101011 ............ ..... ..... @hint_r_i12
target/loongarch: Add preldx instruction Resolve the issue of starting the Loongnix 20.5[1] system failure. Logs: Loading Linux 4.19.0-19-loongson-3 ... Loading initial ramdisk ... PROGRESS CODE: V02010004 I0 PROGRESS CODE: V03101019 I0 Error: unknown opcode. 90000000003a3e6c: 0x382c6d82 [1] http://pkg.loongnix.cn/loongnix/isos/Loongnix-20.5/Loongnix-20.5.cartoon.gui.loongarch64.en.qcow2 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230905123910.3052023-1-gaosong@loongson.cn>
2023-09-05 15:39:10 +03:00
preldx 0011 10000010 11000 ..... ..... ..... @hint_rr
target/loongarch: Add fixed point load/store instruction translation This includes: - LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D} - LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D} - LDPTR.{W/D}, STPTR.{W/D} - PRELD - LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D} - DBAR, IBAR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:57 +03:00
dbar 0011 10000111 00100 ............... @i15
ibar 0011 10000111 00101 ............... @i15
ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2
stptr_w 0010 0101 .............. ..... ..... @rr_i14s2
ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2
stptr_d 0010 0111 .............. ..... ..... @rr_i14s2
ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr
ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr
ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr
ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr
ldle_b 0011 10000111 10100 ..... ..... ..... @rrr
ldle_h 0011 10000111 10101 ..... ..... ..... @rrr
ldle_w 0011 10000111 10110 ..... ..... ..... @rrr
ldle_d 0011 10000111 10111 ..... ..... ..... @rrr
stgt_b 0011 10000111 11000 ..... ..... ..... @rrr
stgt_h 0011 10000111 11001 ..... ..... ..... @rrr
stgt_w 0011 10000111 11010 ..... ..... ..... @rrr
stgt_d 0011 10000111 11011 ..... ..... ..... @rrr
stle_b 0011 10000111 11100 ..... ..... ..... @rrr
stle_h 0011 10000111 11101 ..... ..... ..... @rrr
stle_w 0011 10000111 11110 ..... ..... ..... @rrr
stle_d 0011 10000111 11111 ..... ..... ..... @rrr
target/loongarch: Add fixed point atomic instruction translation This includes: - LL.{W/D}, SC.{W/D} - AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D} - AM{MAX/MIN}[_DB].{WU/DU} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-9-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:58 +03:00
#
# Fixed point atomic instruction
#
ll_w 0010 0000 .............. ..... ..... @rr_i14s2
sc_w 0010 0001 .............. ..... ..... @rr_i14s2
ll_d 0010 0010 .............. ..... ..... @rr_i14s2
sc_d 0010 0011 .............. ..... ..... @rr_i14s2
amswap_w 0011 10000110 00000 ..... ..... ..... @rrr
amswap_d 0011 10000110 00001 ..... ..... ..... @rrr
amadd_w 0011 10000110 00010 ..... ..... ..... @rrr
amadd_d 0011 10000110 00011 ..... ..... ..... @rrr
amand_w 0011 10000110 00100 ..... ..... ..... @rrr
amand_d 0011 10000110 00101 ..... ..... ..... @rrr
amor_w 0011 10000110 00110 ..... ..... ..... @rrr
amor_d 0011 10000110 00111 ..... ..... ..... @rrr
amxor_w 0011 10000110 01000 ..... ..... ..... @rrr
amxor_d 0011 10000110 01001 ..... ..... ..... @rrr
ammax_w 0011 10000110 01010 ..... ..... ..... @rrr
ammax_d 0011 10000110 01011 ..... ..... ..... @rrr
ammin_w 0011 10000110 01100 ..... ..... ..... @rrr
ammin_d 0011 10000110 01101 ..... ..... ..... @rrr
ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr
ammax_du 0011 10000110 01111 ..... ..... ..... @rrr
ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr
ammin_du 0011 10000110 10001 ..... ..... ..... @rrr
amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr
amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr
amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr
amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr
amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr
amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr
amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr
amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr
amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr
amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr
ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr
ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr
ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr
ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr
ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
target/loongarch: Add fixed point extra instruction translation This includes: - CRC[C].W.{B/H/W/D}.W - SYSCALL - BREAK - ASRT{LE/GT}.D - RDTIME{L/H}.W, RDTIME.D - CPUCFG Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:59 +03:00
#
# Fixed point extra instruction
#
crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr
crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr
crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr
crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr
crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr
crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr
crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr
crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr
break 0000 00000010 10100 ............... @i15
syscall 0000 00000010 10110 ............... @i15
asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk
asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk
target/loongarch: Add timer related instructions support. This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-30-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:19 +03:00
rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr
rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr
rdtime_d 0000 00000000 00000 11010 ..... ..... @rr
target/loongarch: Add fixed point extra instruction translation This includes: - CRC[C].W.{B/H/W/D}.W - SYSCALL - BREAK - ASRT{LE/GT}.D - RDTIME{L/H}.W, RDTIME.D - CPUCFG Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:59 +03:00
cpucfg 0000 00000000 00000 11011 ..... ..... @rr
target/loongarch: Add floating point arithmetic instruction translation This includes: - F{ADD/SUB/MUL/DIV}.{S/D} - F{MADD/MSUB/NMADD/NMSUB}.{S/D} - F{MAX/MIN}.{S/D} - F{MAXA/MINA}.{S/D} - F{ABS/NEG}.{S/D} - F{SQRT/RECIP/RSQRT}.{S/D} - F{SCALEB/LOGB/COPYSIGN}.{S/D} - FCLASS.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-11-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:00 +03:00
#
# Floating point arithmetic operation instruction
#
fadd_s 0000 00010000 00001 ..... ..... ..... @fff
fadd_d 0000 00010000 00010 ..... ..... ..... @fff
fsub_s 0000 00010000 00101 ..... ..... ..... @fff
fsub_d 0000 00010000 00110 ..... ..... ..... @fff
fmul_s 0000 00010000 01001 ..... ..... ..... @fff
fmul_d 0000 00010000 01010 ..... ..... ..... @fff
fdiv_s 0000 00010000 01101 ..... ..... ..... @fff
fdiv_d 0000 00010000 01110 ..... ..... ..... @fff
fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff
fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff
fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff
fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff
fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff
fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff
fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff
fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff
fmax_s 0000 00010000 10001 ..... ..... ..... @fff
fmax_d 0000 00010000 10010 ..... ..... ..... @fff
fmin_s 0000 00010000 10101 ..... ..... ..... @fff
fmin_d 0000 00010000 10110 ..... ..... ..... @fff
fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff
fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff
fmina_s 0000 00010000 11101 ..... ..... ..... @fff
fmina_d 0000 00010000 11110 ..... ..... ..... @fff
fabs_s 0000 00010001 01000 00001 ..... ..... @ff
fabs_d 0000 00010001 01000 00010 ..... ..... @ff
fneg_s 0000 00010001 01000 00101 ..... ..... @ff
fneg_d 0000 00010001 01000 00110 ..... ..... @ff
fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff
fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff
frecip_s 0000 00010001 01000 10101 ..... ..... @ff
frecip_d 0000 00010001 01000 10110 ..... ..... @ff
frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff
frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff
fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff
fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff
flogb_s 0000 00010001 01000 01001 ..... ..... @ff
flogb_d 0000 00010001 01000 01010 ..... ..... @ff
fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff
fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff
fclass_s 0000 00010001 01000 01101 ..... ..... @ff
fclass_d 0000 00010001 01000 01110 ..... ..... @ff
target/loongarch: Add floating point comparison instruction translation This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-12-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:01 +03:00
#
# Floating point compare instruction
#
fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond
fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond
target/loongarch: Add floating point conversion instruction translation This includes: - FCVT.S.D, FCVT.D.S - FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D} - FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D} - FRINT.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-13-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:02 +03:00
#
# Floating point conversion instruction
#
fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff
fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff
ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff
ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff
ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff
ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff
ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff
ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff
ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff
ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff
ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff
ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff
ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff
ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff
ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff
ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff
ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff
ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff
ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff
ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff
ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff
ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff
ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff
ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff
ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff
ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff
frint_s 0000 00010001 11100 10001 ..... ..... @ff
frint_d 0000 00010001 11100 10010 ..... ..... @ff
target/loongarch: Add floating point move instruction translation This includes: - FMOV.{S/D} - FSEL - MOVGR2FR.{W/D}, MOVGR2FRH.W - MOVFR2GR.{S/D}, MOVFRH2GR.S - MOVGR2FCSR, MOVFCSR2GR - MOVFR2CF, MOVCF2FR - MOVGR2CF, MOVCF2GR Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-14-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:03 +03:00
#
# Floating point move instruction
#
fmov_s 0000 00010001 01001 00101 ..... ..... @ff
fmov_d 0000 00010001 01001 00110 ..... ..... @ff
fsel 0000 11010000 00 ... ..... ..... ..... @fffc
movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr
movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr
movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr
movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf
movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf
movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf
movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r
movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs
movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr
movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc
target/loongarch: Add floating point load/store instruction translation This includes: - FLD.{S/D}, FST.{S/D} - FLDX.{S/D}, FSTX.{S/D} - FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-15-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:04 +03:00
#
# Floating point load/store instruction
#
fld_s 0010 101100 ............ ..... ..... @fr_i12
fst_s 0010 101101 ............ ..... ..... @fr_i12
fld_d 0010 101110 ............ ..... ..... @fr_i12
fst_d 0010 101111 ............ ..... ..... @fr_i12
fldx_s 0011 10000011 00000 ..... ..... ..... @frr
fldx_d 0011 10000011 01000 ..... ..... ..... @frr
fstx_s 0011 10000011 10000 ..... ..... ..... @frr
fstx_d 0011 10000011 11000 ..... ..... ..... @frr
fldgt_s 0011 10000111 01000 ..... ..... ..... @frr
fldgt_d 0011 10000111 01001 ..... ..... ..... @frr
fldle_s 0011 10000111 01010 ..... ..... ..... @frr
fldle_d 0011 10000111 01011 ..... ..... ..... @frr
fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
fstle_s 0011 10000111 01110 ..... ..... ..... @frr
fstle_d 0011 10000111 01111 ..... ..... ..... @frr
target/loongarch: Add branch instruction translation This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:05 +03:00
#
# Branch instructions
#
beqz 0100 00 ................ ..... ..... @r_offs21
bnez 0100 01 ................ ..... ..... @r_offs21
bceqz 0100 10 ................ 00 ... ..... @c_offs21
bcnez 0100 10 ................ 01 ... ..... @c_offs21
target/loongarch: Disassemble jirl properly While jirl shares the same instruction format as bne etc, it is not assembled the same. In particular, rd is printed first not second and the immediate is not pc-relative. Decode into the arg_rr_i structure, which prints correctly. This changes the "offs" member to "imm", to update translate. Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-18 03:32:38 +03:00
jirl 0100 11 ................ ..... ..... @rr_i16s2
target/loongarch: Add branch instruction translation This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:05 +03:00
b 0101 00 .......................... @offs26
bl 0101 01 .......................... @offs26
beq 0101 10 ................ ..... ..... @rr_offs16
bne 0101 11 ................ ..... ..... @rr_offs16
blt 0110 00 ................ ..... ..... @rr_offs16
bge 0110 01 ................ ..... ..... @rr_offs16
bltu 0110 10 ................ ..... ..... @rr_offs16
bgeu 0110 11 ................ ..... ..... @rr_offs16
target/loongarch: Add LoongArch CSR instruction This includes: - CSRRD - CSRWR - CSRXCHG Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-26-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:15 +03:00
#
# Core instructions
#
{
csrrd 0000 0100 .............. 00000 ..... @r_csr
csrwr 0000 0100 .............. 00001 ..... @r_csr
csrxchg 0000 0100 .............. ..... ..... @rr_csr
}
target/loongarch: Add LoongArch IOCSR instruction This includes: - IOCSR{RD/WR}.{B/H/W/D} Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-27-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:16 +03:00
iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr
iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr
iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr
iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr
iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr
iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr
iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr
iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr
target/loongarch: Add TLB instruction support This includes: - TLBSRCH - TLBRD - TLBWR - TLBFILL - TLBCLR - TLBFLUSH - INVTLB Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-28-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:17 +03:00
tlbsrch 0000 01100100 10000 01010 00000 00000 @empty
tlbrd 0000 01100100 10000 01011 00000 00000 @empty
tlbwr 0000 01100100 10000 01100 00000 00000 @empty
tlbfill 0000 01100100 10000 01101 00000 00000 @empty
tlbclr 0000 01100100 10000 01000 00000 00000 @empty
tlbflush 0000 01100100 10000 01001 00000 00000 @empty
invtlb 0000 01100100 10011 ..... ..... ..... @i_rr
target/loongarch: Add other core instructions support This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-29-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:43:18 +03:00
cacop 0000 011000 ............ ..... ..... @cop_r_i
lddir 0000 01100100 00 ........ ..... ..... @rr_ui8
ldpte 0000 01100100 01 ........ ..... 00000 @j_i
ertn 0000 01100100 10000 01110 00000 00000 @empty
idle 0000 01100100 10001 ............... @i15
dbcl 0000 00000010 10101 ............... @i15
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
target/loongarch: Implement vld vst This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-04 15:28:07 +03:00
#
# LSX Fields
#
%i9s3 10:s9 !function=shl_3
%i10s2 10:s10 !function=shl_2
%i11s1 10:s11 !function=shl_1
%i8s3 10:s8 !function=shl_3
%i8s2 10:s8 !function=shl_2
%i8s1 10:s8 !function=shl_1
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
#
# LSX Argument sets
#
target/loongarch: Implement vneg This patch includes; - VNEG.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-7-gaosong@loongson.cn>
2023-05-04 15:27:32 +03:00
&vv vd vj
target/loongarch: Implement vbitsel vset This patch includes: - VBITSEL.V; - VBITSELI.B; - VSET{EQZ/NEZ}.V; - VSETANYEQZ.{B/H/W/D}; - VSETALLNEZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
2023-05-04 15:28:03 +03:00
&cv cd vj
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
&vvv vd vj vk
target/loongarch: Implement vaddi/vsubi This patch includes: - VADDI.{B/H/W/D}U; - VSUBI.{B/H/W/D}U. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-6-gaosong@loongson.cn>
2023-05-04 15:27:31 +03:00
&vv_i vd vj imm
target/loongarch: Implement LSX fpu arith instructions This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
2023-05-04 15:27:59 +03:00
&vvvv vd vj vk va
target/loongarch: Implement vfcmp This patch includes: - VFCMP.cond.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-37-gaosong@loongson.cn>
2023-05-04 15:28:02 +03:00
&vvv_fcond vd vj vk fcond
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr This patch includes: - VINSGR2VR.{B/H/W/D}; - VPICKVE2GR.{B/H/W/D}[U]; - VREPLGR2VR.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
2023-05-04 15:28:04 +03:00
&vr_i vd rj imm
&rv_i rd vj imm
&vr vd rj
target/loongarch: Implement vreplve vpack vpick This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
2023-05-04 15:28:05 +03:00
&vvr vd vj rk
target/loongarch: Implement vld vst This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-04 15:28:07 +03:00
&vrr vd rj rk
&vr_ii vd rj imm imm2
target/loongarch: Implement vldi This patch includes: - VLDI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-43-gaosong@loongson.cn>
2023-05-04 15:28:08 +03:00
&v_i vd imm
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
#
# LSX Formats
#
target/loongarch: Implement vneg This patch includes; - VNEG.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-7-gaosong@loongson.cn>
2023-05-04 15:27:32 +03:00
@vv .... ........ ..... ..... vj:5 vd:5 &vv
target/loongarch: Implement vbitsel vset This patch includes: - VBITSEL.V; - VBITSELI.B; - VSET{EQZ/NEZ}.V; - VSETANYEQZ.{B/H/W/D}; - VSETALLNEZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
2023-05-04 15:28:03 +03:00
@cv .... ........ ..... ..... vj:5 .. cd:3 &cv
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
target/loongarch: Implement vreplve vpack vpick This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
2023-05-04 15:28:05 +03:00
@vv_ui1 .... ........ ..... .... imm:1 vj:5 vd:5 &vv_i
@vv_ui2 .... ........ ..... ... imm:2 vj:5 vd:5 &vv_i
target/loongarch: Implement vsat This patch includes: - VSAT.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-18-gaosong@loongson.cn>
2023-05-04 15:27:43 +03:00
@vv_ui3 .... ........ ..... .. imm:3 vj:5 vd:5 &vv_i
@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
target/loongarch: Implement vaddi/vsubi This patch includes: - VADDI.{B/H/W/D}U; - VSUBI.{B/H/W/D}U. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-6-gaosong@loongson.cn>
2023-05-04 15:27:31 +03:00
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
target/loongarch: Implement vsat This patch includes: - VSAT.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-18-gaosong@loongson.cn>
2023-05-04 15:27:43 +03:00
@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i
target/loongarch: Implement vsrln vsran This patch includes: - VSRLN.{B.H/H.W/W.D}; - VSRAN.{B.H/H.W/W.D}; - VSRLNI.{B.H/H.W/W.D/D.Q}; - VSRANI.{B.H/H.W/W.D/D.Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-26-gaosong@loongson.cn>
2023-05-04 15:27:51 +03:00
@vv_ui7 .... ........ ... imm:7 vj:5 vd:5 &vv_i
target/loongarch: Implement LSX logic instructions This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-22-gaosong@loongson.cn>
2023-05-04 15:27:47 +03:00
@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
target/loongarch: Implement vmax/vmin This patch includes: - VMAX[I].{B/H/W/D}[U]; - VMIN[I].{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-14-gaosong@loongson.cn>
2023-05-04 15:27:39 +03:00
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
target/loongarch: Implement LSX fpu arith instructions This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
2023-05-04 15:27:59 +03:00
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv
target/loongarch: Implement vfcmp This patch includes: - VFCMP.cond.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-37-gaosong@loongson.cn>
2023-05-04 15:28:02 +03:00
@vvv_fcond .... ........ fcond:5 vk:5 vj:5 vd:5 &vvv_fcond
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr This patch includes: - VINSGR2VR.{B/H/W/D}; - VPICKVE2GR.{B/H/W/D}[U]; - VREPLGR2VR.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
2023-05-04 15:28:04 +03:00
@vr_ui4 .... ........ ..... . imm:4 rj:5 vd:5 &vr_i
@vr_ui3 .... ........ ..... .. imm:3 rj:5 vd:5 &vr_i
@vr_ui2 .... ........ ..... ... imm:2 rj:5 vd:5 &vr_i
@vr_ui1 .... ........ ..... .... imm:1 rj:5 vd:5 &vr_i
@rv_ui4 .... ........ ..... . imm:4 vj:5 rd:5 &rv_i
@rv_ui3 .... ........ ..... .. imm:3 vj:5 rd:5 &rv_i
@rv_ui2 .... ........ ..... ... imm:2 vj:5 rd:5 &rv_i
@rv_ui1 .... ........ ..... .... imm:1 vj:5 rd:5 &rv_i
@vr .... ........ ..... ..... rj:5 vd:5 &vr
target/loongarch: Implement vreplve vpack vpick This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
2023-05-04 15:28:05 +03:00
@vvr .... ........ ..... rk:5 vj:5 vd:5 &vvr
target/loongarch: Implement vld vst This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-04 15:28:07 +03:00
@vr_i9 .... ........ . ......... rj:5 vd:5 &vr_i imm=%i9s3
@vr_i10 .... ........ .......... rj:5 vd:5 &vr_i imm=%i10s2
@vr_i11 .... ....... ........... rj:5 vd:5 &vr_i imm=%i11s1
@vr_i12 .... ...... imm:s12 rj:5 vd:5 &vr_i
@vr_i8i1 .... ........ . imm2:1 ........ rj:5 vd:5 &vr_ii imm=%i8s3
@vr_i8i2 .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s2
@vr_i8i3 .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s1
@vr_i8i4 .... ...... imm2:4 imm:s8 rj:5 vd:5 &vr_ii
target/loongarch: Implement xvld xvst This patch includes: - XVLD[X], XVST[X]; - XVLDREPL.{B/H/W/D}; - XVSTELM.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-56-gaosong@loongson.cn>
2023-09-14 05:26:43 +03:00
@vr_i8i2x .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s3
@vr_i8i3x .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s2
@vr_i8i4x .... ...... imm2:4 ........ rj:5 vd:5 &vr_ii imm=%i8s1
@vr_i8i5x .... ..... imm2:5 imm:s8 rj:5 vd:5 &vr_ii
target/loongarch: Implement vld vst This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-04 15:28:07 +03:00
@vrr .... ........ ..... rk:5 rj:5 vd:5 &vrr
target/loongarch: Implement vldi This patch includes: - VLDI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-43-gaosong@loongson.cn>
2023-05-04 15:28:08 +03:00
@v_i13 .... ........ .. imm:13 vd:5 &v_i
target/loongarch: Implement vadd/vsub This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
2023-05-04 15:27:30 +03:00
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
vadd_w 0111 00000000 10110 ..... ..... ..... @vvv
vadd_d 0111 00000000 10111 ..... ..... ..... @vvv
vadd_q 0111 00010010 11010 ..... ..... ..... @vvv
vsub_b 0111 00000000 11000 ..... ..... ..... @vvv
vsub_h 0111 00000000 11001 ..... ..... ..... @vvv
vsub_w 0111 00000000 11010 ..... ..... ..... @vvv
vsub_d 0111 00000000 11011 ..... ..... ..... @vvv
vsub_q 0111 00010010 11011 ..... ..... ..... @vvv
target/loongarch: Implement vaddi/vsubi This patch includes: - VADDI.{B/H/W/D}U; - VSUBI.{B/H/W/D}U. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-6-gaosong@loongson.cn>
2023-05-04 15:27:31 +03:00
vaddi_bu 0111 00101000 10100 ..... ..... ..... @vv_ui5
vaddi_hu 0111 00101000 10101 ..... ..... ..... @vv_ui5
vaddi_wu 0111 00101000 10110 ..... ..... ..... @vv_ui5
vaddi_du 0111 00101000 10111 ..... ..... ..... @vv_ui5
vsubi_bu 0111 00101000 11000 ..... ..... ..... @vv_ui5
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5
target/loongarch: Implement vneg This patch includes; - VNEG.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-7-gaosong@loongson.cn>
2023-05-04 15:27:32 +03:00
vneg_b 0111 00101001 11000 01100 ..... ..... @vv
vneg_h 0111 00101001 11000 01101 ..... ..... @vv
vneg_w 0111 00101001 11000 01110 ..... ..... @vv
vneg_d 0111 00101001 11000 01111 ..... ..... @vv
target/loongarch: Implement vsadd/vssub This patch includes: - VSADD.{B/H/W/D}[U]; - VSSUB.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-8-gaosong@loongson.cn>
2023-05-04 15:27:33 +03:00
vsadd_b 0111 00000100 01100 ..... ..... ..... @vvv
vsadd_h 0111 00000100 01101 ..... ..... ..... @vvv
vsadd_w 0111 00000100 01110 ..... ..... ..... @vvv
vsadd_d 0111 00000100 01111 ..... ..... ..... @vvv
vsadd_bu 0111 00000100 10100 ..... ..... ..... @vvv
vsadd_hu 0111 00000100 10101 ..... ..... ..... @vvv
vsadd_wu 0111 00000100 10110 ..... ..... ..... @vvv
vsadd_du 0111 00000100 10111 ..... ..... ..... @vvv
vssub_b 0111 00000100 10000 ..... ..... ..... @vvv
vssub_h 0111 00000100 10001 ..... ..... ..... @vvv
vssub_w 0111 00000100 10010 ..... ..... ..... @vvv
vssub_d 0111 00000100 10011 ..... ..... ..... @vvv
vssub_bu 0111 00000100 11000 ..... ..... ..... @vvv
vssub_hu 0111 00000100 11001 ..... ..... ..... @vvv
vssub_wu 0111 00000100 11010 ..... ..... ..... @vvv
vssub_du 0111 00000100 11011 ..... ..... ..... @vvv
target/loongarch: Implement vhaddw/vhsubw This patch includes: - VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-9-gaosong@loongson.cn>
2023-05-04 15:27:34 +03:00
vhaddw_h_b 0111 00000101 01000 ..... ..... ..... @vvv
vhaddw_w_h 0111 00000101 01001 ..... ..... ..... @vvv
vhaddw_d_w 0111 00000101 01010 ..... ..... ..... @vvv
vhaddw_q_d 0111 00000101 01011 ..... ..... ..... @vvv
vhaddw_hu_bu 0111 00000101 10000 ..... ..... ..... @vvv
vhaddw_wu_hu 0111 00000101 10001 ..... ..... ..... @vvv
vhaddw_du_wu 0111 00000101 10010 ..... ..... ..... @vvv
vhaddw_qu_du 0111 00000101 10011 ..... ..... ..... @vvv
vhsubw_h_b 0111 00000101 01100 ..... ..... ..... @vvv
vhsubw_w_h 0111 00000101 01101 ..... ..... ..... @vvv
vhsubw_d_w 0111 00000101 01110 ..... ..... ..... @vvv
vhsubw_q_d 0111 00000101 01111 ..... ..... ..... @vvv
vhsubw_hu_bu 0111 00000101 10100 ..... ..... ..... @vvv
vhsubw_wu_hu 0111 00000101 10101 ..... ..... ..... @vvv
vhsubw_du_wu 0111 00000101 10110 ..... ..... ..... @vvv
vhsubw_qu_du 0111 00000101 10111 ..... ..... ..... @vvv
target/loongarch: Implement vaddw/vsubw This patch includes: - VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-10-gaosong@loongson.cn>
2023-05-04 15:27:35 +03:00
vaddwev_h_b 0111 00000001 11100 ..... ..... ..... @vvv
vaddwev_w_h 0111 00000001 11101 ..... ..... ..... @vvv
vaddwev_d_w 0111 00000001 11110 ..... ..... ..... @vvv
vaddwev_q_d 0111 00000001 11111 ..... ..... ..... @vvv
vaddwod_h_b 0111 00000010 00100 ..... ..... ..... @vvv
vaddwod_w_h 0111 00000010 00101 ..... ..... ..... @vvv
vaddwod_d_w 0111 00000010 00110 ..... ..... ..... @vvv
vaddwod_q_d 0111 00000010 00111 ..... ..... ..... @vvv
vsubwev_h_b 0111 00000010 00000 ..... ..... ..... @vvv
vsubwev_w_h 0111 00000010 00001 ..... ..... ..... @vvv
vsubwev_d_w 0111 00000010 00010 ..... ..... ..... @vvv
vsubwev_q_d 0111 00000010 00011 ..... ..... ..... @vvv
vsubwod_h_b 0111 00000010 01000 ..... ..... ..... @vvv
vsubwod_w_h 0111 00000010 01001 ..... ..... ..... @vvv
vsubwod_d_w 0111 00000010 01010 ..... ..... ..... @vvv
vsubwod_q_d 0111 00000010 01011 ..... ..... ..... @vvv
vaddwev_h_bu 0111 00000010 11100 ..... ..... ..... @vvv
vaddwev_w_hu 0111 00000010 11101 ..... ..... ..... @vvv
vaddwev_d_wu 0111 00000010 11110 ..... ..... ..... @vvv
vaddwev_q_du 0111 00000010 11111 ..... ..... ..... @vvv
vaddwod_h_bu 0111 00000011 00100 ..... ..... ..... @vvv
vaddwod_w_hu 0111 00000011 00101 ..... ..... ..... @vvv
vaddwod_d_wu 0111 00000011 00110 ..... ..... ..... @vvv
vaddwod_q_du 0111 00000011 00111 ..... ..... ..... @vvv
vsubwev_h_bu 0111 00000011 00000 ..... ..... ..... @vvv
vsubwev_w_hu 0111 00000011 00001 ..... ..... ..... @vvv
vsubwev_d_wu 0111 00000011 00010 ..... ..... ..... @vvv
vsubwev_q_du 0111 00000011 00011 ..... ..... ..... @vvv
vsubwod_h_bu 0111 00000011 01000 ..... ..... ..... @vvv
vsubwod_w_hu 0111 00000011 01001 ..... ..... ..... @vvv
vsubwod_d_wu 0111 00000011 01010 ..... ..... ..... @vvv
vsubwod_q_du 0111 00000011 01011 ..... ..... ..... @vvv
vaddwev_h_bu_b 0111 00000011 11100 ..... ..... ..... @vvv
vaddwev_w_hu_h 0111 00000011 11101 ..... ..... ..... @vvv
vaddwev_d_wu_w 0111 00000011 11110 ..... ..... ..... @vvv
vaddwev_q_du_d 0111 00000011 11111 ..... ..... ..... @vvv
vaddwod_h_bu_b 0111 00000100 00000 ..... ..... ..... @vvv
vaddwod_w_hu_h 0111 00000100 00001 ..... ..... ..... @vvv
vaddwod_d_wu_w 0111 00000100 00010 ..... ..... ..... @vvv
vaddwod_q_du_d 0111 00000100 00011 ..... ..... ..... @vvv
target/loongarch: Implement vavg/vavgr This patch includes: - VAVG.{B/H/W/D}[U]; - VAVGR.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-11-gaosong@loongson.cn>
2023-05-04 15:27:36 +03:00
vavg_b 0111 00000110 01000 ..... ..... ..... @vvv
vavg_h 0111 00000110 01001 ..... ..... ..... @vvv
vavg_w 0111 00000110 01010 ..... ..... ..... @vvv
vavg_d 0111 00000110 01011 ..... ..... ..... @vvv
vavg_bu 0111 00000110 01100 ..... ..... ..... @vvv
vavg_hu 0111 00000110 01101 ..... ..... ..... @vvv
vavg_wu 0111 00000110 01110 ..... ..... ..... @vvv
vavg_du 0111 00000110 01111 ..... ..... ..... @vvv
vavgr_b 0111 00000110 10000 ..... ..... ..... @vvv
vavgr_h 0111 00000110 10001 ..... ..... ..... @vvv
vavgr_w 0111 00000110 10010 ..... ..... ..... @vvv
vavgr_d 0111 00000110 10011 ..... ..... ..... @vvv
vavgr_bu 0111 00000110 10100 ..... ..... ..... @vvv
vavgr_hu 0111 00000110 10101 ..... ..... ..... @vvv
vavgr_wu 0111 00000110 10110 ..... ..... ..... @vvv
vavgr_du 0111 00000110 10111 ..... ..... ..... @vvv
target/loongarch: Implement vabsd This patch includes: - VABSD.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-12-gaosong@loongson.cn>
2023-05-04 15:27:37 +03:00
vabsd_b 0111 00000110 00000 ..... ..... ..... @vvv
vabsd_h 0111 00000110 00001 ..... ..... ..... @vvv
vabsd_w 0111 00000110 00010 ..... ..... ..... @vvv
vabsd_d 0111 00000110 00011 ..... ..... ..... @vvv
vabsd_bu 0111 00000110 00100 ..... ..... ..... @vvv
vabsd_hu 0111 00000110 00101 ..... ..... ..... @vvv
vabsd_wu 0111 00000110 00110 ..... ..... ..... @vvv
vabsd_du 0111 00000110 00111 ..... ..... ..... @vvv
target/loongarch: Implement vadda This patch includes: - VADDA.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-13-gaosong@loongson.cn>
2023-05-04 15:27:38 +03:00
vadda_b 0111 00000101 11000 ..... ..... ..... @vvv
vadda_h 0111 00000101 11001 ..... ..... ..... @vvv
vadda_w 0111 00000101 11010 ..... ..... ..... @vvv
vadda_d 0111 00000101 11011 ..... ..... ..... @vvv
target/loongarch: Implement vmax/vmin This patch includes: - VMAX[I].{B/H/W/D}[U]; - VMIN[I].{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-14-gaosong@loongson.cn>
2023-05-04 15:27:39 +03:00
vmax_b 0111 00000111 00000 ..... ..... ..... @vvv
vmax_h 0111 00000111 00001 ..... ..... ..... @vvv
vmax_w 0111 00000111 00010 ..... ..... ..... @vvv
vmax_d 0111 00000111 00011 ..... ..... ..... @vvv
vmaxi_b 0111 00101001 00000 ..... ..... ..... @vv_i5
vmaxi_h 0111 00101001 00001 ..... ..... ..... @vv_i5
vmaxi_w 0111 00101001 00010 ..... ..... ..... @vv_i5
vmaxi_d 0111 00101001 00011 ..... ..... ..... @vv_i5
vmax_bu 0111 00000111 01000 ..... ..... ..... @vvv
vmax_hu 0111 00000111 01001 ..... ..... ..... @vvv
vmax_wu 0111 00000111 01010 ..... ..... ..... @vvv
vmax_du 0111 00000111 01011 ..... ..... ..... @vvv
vmaxi_bu 0111 00101001 01000 ..... ..... ..... @vv_ui5
vmaxi_hu 0111 00101001 01001 ..... ..... ..... @vv_ui5
vmaxi_wu 0111 00101001 01010 ..... ..... ..... @vv_ui5
vmaxi_du 0111 00101001 01011 ..... ..... ..... @vv_ui5
vmin_b 0111 00000111 00100 ..... ..... ..... @vvv
vmin_h 0111 00000111 00101 ..... ..... ..... @vvv
vmin_w 0111 00000111 00110 ..... ..... ..... @vvv
vmin_d 0111 00000111 00111 ..... ..... ..... @vvv
vmini_b 0111 00101001 00100 ..... ..... ..... @vv_i5
vmini_h 0111 00101001 00101 ..... ..... ..... @vv_i5
vmini_w 0111 00101001 00110 ..... ..... ..... @vv_i5
vmini_d 0111 00101001 00111 ..... ..... ..... @vv_i5
vmin_bu 0111 00000111 01100 ..... ..... ..... @vvv
vmin_hu 0111 00000111 01101 ..... ..... ..... @vvv
vmin_wu 0111 00000111 01110 ..... ..... ..... @vvv
vmin_du 0111 00000111 01111 ..... ..... ..... @vvv
vmini_bu 0111 00101001 01100 ..... ..... ..... @vv_ui5
vmini_hu 0111 00101001 01101 ..... ..... ..... @vv_ui5
vmini_wu 0111 00101001 01110 ..... ..... ..... @vv_ui5
vmini_du 0111 00101001 01111 ..... ..... ..... @vv_ui5
target/loongarch: Implement vmul/vmuh/vmulw{ev/od} This patch includes: - VMUL.{B/H/W/D}; - VMUH.{B/H/W/D}[U]; - VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-15-gaosong@loongson.cn>
2023-05-04 15:27:40 +03:00
vmul_b 0111 00001000 01000 ..... ..... ..... @vvv
vmul_h 0111 00001000 01001 ..... ..... ..... @vvv
vmul_w 0111 00001000 01010 ..... ..... ..... @vvv
vmul_d 0111 00001000 01011 ..... ..... ..... @vvv
vmuh_b 0111 00001000 01100 ..... ..... ..... @vvv
vmuh_h 0111 00001000 01101 ..... ..... ..... @vvv
vmuh_w 0111 00001000 01110 ..... ..... ..... @vvv
vmuh_d 0111 00001000 01111 ..... ..... ..... @vvv
vmuh_bu 0111 00001000 10000 ..... ..... ..... @vvv
vmuh_hu 0111 00001000 10001 ..... ..... ..... @vvv
vmuh_wu 0111 00001000 10010 ..... ..... ..... @vvv
vmuh_du 0111 00001000 10011 ..... ..... ..... @vvv
vmulwev_h_b 0111 00001001 00000 ..... ..... ..... @vvv
vmulwev_w_h 0111 00001001 00001 ..... ..... ..... @vvv
vmulwev_d_w 0111 00001001 00010 ..... ..... ..... @vvv
vmulwev_q_d 0111 00001001 00011 ..... ..... ..... @vvv
vmulwod_h_b 0111 00001001 00100 ..... ..... ..... @vvv
vmulwod_w_h 0111 00001001 00101 ..... ..... ..... @vvv
vmulwod_d_w 0111 00001001 00110 ..... ..... ..... @vvv
vmulwod_q_d 0111 00001001 00111 ..... ..... ..... @vvv
vmulwev_h_bu 0111 00001001 10000 ..... ..... ..... @vvv
vmulwev_w_hu 0111 00001001 10001 ..... ..... ..... @vvv
vmulwev_d_wu 0111 00001001 10010 ..... ..... ..... @vvv
vmulwev_q_du 0111 00001001 10011 ..... ..... ..... @vvv
vmulwod_h_bu 0111 00001001 10100 ..... ..... ..... @vvv
vmulwod_w_hu 0111 00001001 10101 ..... ..... ..... @vvv
vmulwod_d_wu 0111 00001001 10110 ..... ..... ..... @vvv
vmulwod_q_du 0111 00001001 10111 ..... ..... ..... @vvv
vmulwev_h_bu_b 0111 00001010 00000 ..... ..... ..... @vvv
vmulwev_w_hu_h 0111 00001010 00001 ..... ..... ..... @vvv
vmulwev_d_wu_w 0111 00001010 00010 ..... ..... ..... @vvv
vmulwev_q_du_d 0111 00001010 00011 ..... ..... ..... @vvv
vmulwod_h_bu_b 0111 00001010 00100 ..... ..... ..... @vvv
vmulwod_w_hu_h 0111 00001010 00101 ..... ..... ..... @vvv
vmulwod_d_wu_w 0111 00001010 00110 ..... ..... ..... @vvv
vmulwod_q_du_d 0111 00001010 00111 ..... ..... ..... @vvv
target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od} This patch includes: - VMADD.{B/H/W/D}; - VMSUB.{B/H/W/D}; - VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-16-gaosong@loongson.cn>
2023-05-04 15:27:41 +03:00
vmadd_b 0111 00001010 10000 ..... ..... ..... @vvv
vmadd_h 0111 00001010 10001 ..... ..... ..... @vvv
vmadd_w 0111 00001010 10010 ..... ..... ..... @vvv
vmadd_d 0111 00001010 10011 ..... ..... ..... @vvv
vmsub_b 0111 00001010 10100 ..... ..... ..... @vvv
vmsub_h 0111 00001010 10101 ..... ..... ..... @vvv
vmsub_w 0111 00001010 10110 ..... ..... ..... @vvv
vmsub_d 0111 00001010 10111 ..... ..... ..... @vvv
vmaddwev_h_b 0111 00001010 11000 ..... ..... ..... @vvv
vmaddwev_w_h 0111 00001010 11001 ..... ..... ..... @vvv
vmaddwev_d_w 0111 00001010 11010 ..... ..... ..... @vvv
vmaddwev_q_d 0111 00001010 11011 ..... ..... ..... @vvv
vmaddwod_h_b 0111 00001010 11100 ..... ..... ..... @vvv
vmaddwod_w_h 0111 00001010 11101 ..... ..... ..... @vvv
vmaddwod_d_w 0111 00001010 11110 ..... ..... ..... @vvv
vmaddwod_q_d 0111 00001010 11111 ..... ..... ..... @vvv
vmaddwev_h_bu 0111 00001011 01000 ..... ..... ..... @vvv
vmaddwev_w_hu 0111 00001011 01001 ..... ..... ..... @vvv
vmaddwev_d_wu 0111 00001011 01010 ..... ..... ..... @vvv
vmaddwev_q_du 0111 00001011 01011 ..... ..... ..... @vvv
vmaddwod_h_bu 0111 00001011 01100 ..... ..... ..... @vvv
vmaddwod_w_hu 0111 00001011 01101 ..... ..... ..... @vvv
vmaddwod_d_wu 0111 00001011 01110 ..... ..... ..... @vvv
vmaddwod_q_du 0111 00001011 01111 ..... ..... ..... @vvv
vmaddwev_h_bu_b 0111 00001011 11000 ..... ..... ..... @vvv
vmaddwev_w_hu_h 0111 00001011 11001 ..... ..... ..... @vvv
vmaddwev_d_wu_w 0111 00001011 11010 ..... ..... ..... @vvv
vmaddwev_q_du_d 0111 00001011 11011 ..... ..... ..... @vvv
vmaddwod_h_bu_b 0111 00001011 11100 ..... ..... ..... @vvv
vmaddwod_w_hu_h 0111 00001011 11101 ..... ..... ..... @vvv
vmaddwod_d_wu_w 0111 00001011 11110 ..... ..... ..... @vvv
vmaddwod_q_du_d 0111 00001011 11111 ..... ..... ..... @vvv
target/loongarch: Implement vdiv/vmod This patch includes: - VDIV.{B/H/W/D}[U]; - VMOD.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-17-gaosong@loongson.cn>
2023-05-04 15:27:42 +03:00
vdiv_b 0111 00001110 00000 ..... ..... ..... @vvv
vdiv_h 0111 00001110 00001 ..... ..... ..... @vvv
vdiv_w 0111 00001110 00010 ..... ..... ..... @vvv
vdiv_d 0111 00001110 00011 ..... ..... ..... @vvv
vdiv_bu 0111 00001110 01000 ..... ..... ..... @vvv
vdiv_hu 0111 00001110 01001 ..... ..... ..... @vvv
vdiv_wu 0111 00001110 01010 ..... ..... ..... @vvv
vdiv_du 0111 00001110 01011 ..... ..... ..... @vvv
vmod_b 0111 00001110 00100 ..... ..... ..... @vvv
vmod_h 0111 00001110 00101 ..... ..... ..... @vvv
vmod_w 0111 00001110 00110 ..... ..... ..... @vvv
vmod_d 0111 00001110 00111 ..... ..... ..... @vvv
vmod_bu 0111 00001110 01100 ..... ..... ..... @vvv
vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv
vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv
vmod_du 0111 00001110 01111 ..... ..... ..... @vvv
target/loongarch: Implement vsat This patch includes: - VSAT.{B/H/W/D}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-18-gaosong@loongson.cn>
2023-05-04 15:27:43 +03:00
vsat_b 0111 00110010 01000 01 ... ..... ..... @vv_ui3
vsat_h 0111 00110010 01000 1 .... ..... ..... @vv_ui4
vsat_w 0111 00110010 01001 ..... ..... ..... @vv_ui5
vsat_d 0111 00110010 0101 ...... ..... ..... @vv_ui6
vsat_bu 0111 00110010 10000 01 ... ..... ..... @vv_ui3
vsat_hu 0111 00110010 10000 1 .... ..... ..... @vv_ui4
vsat_wu 0111 00110010 10001 ..... ..... ..... @vv_ui5
vsat_du 0111 00110010 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement vexth This patch includes: - VEXTH.{H.B/W.H/D.W/Q.D}; - VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-19-gaosong@loongson.cn>
2023-05-04 15:27:44 +03:00
vexth_h_b 0111 00101001 11101 11000 ..... ..... @vv
vexth_w_h 0111 00101001 11101 11001 ..... ..... @vv
vexth_d_w 0111 00101001 11101 11010 ..... ..... @vv
vexth_q_d 0111 00101001 11101 11011 ..... ..... @vv
vexth_hu_bu 0111 00101001 11101 11100 ..... ..... @vv
vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv
vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv
vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv
target/loongarch: Implement vsigncov This patch includes: - VSIGNCOV.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-20-gaosong@loongson.cn>
2023-05-04 15:27:45 +03:00
vsigncov_b 0111 00010010 11100 ..... ..... ..... @vvv
vsigncov_h 0111 00010010 11101 ..... ..... ..... @vvv
vsigncov_w 0111 00010010 11110 ..... ..... ..... @vvv
vsigncov_d 0111 00010010 11111 ..... ..... ..... @vvv
target/loongarch: Implement vmskltz/vmskgez/vmsknz This patch includes: - VMSKLTZ.{B/H/W/D}; - VMSKGEZ.B; - VMSKNZ.B. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-21-gaosong@loongson.cn>
2023-05-04 15:27:46 +03:00
vmskltz_b 0111 00101001 11000 10000 ..... ..... @vv
vmskltz_h 0111 00101001 11000 10001 ..... ..... @vv
vmskltz_w 0111 00101001 11000 10010 ..... ..... @vv
vmskltz_d 0111 00101001 11000 10011 ..... ..... @vv
vmskgez_b 0111 00101001 11000 10100 ..... ..... @vv
vmsknz_b 0111 00101001 11000 11000 ..... ..... @vv
target/loongarch: Implement LSX logic instructions This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-22-gaosong@loongson.cn>
2023-05-04 15:27:47 +03:00
target/loongarch: Implement vldi This patch includes: - VLDI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-43-gaosong@loongson.cn>
2023-05-04 15:28:08 +03:00
vldi 0111 00111110 00 ............. ..... @v_i13
target/loongarch: Implement LSX logic instructions This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-22-gaosong@loongson.cn>
2023-05-04 15:27:47 +03:00
vand_v 0111 00010010 01100 ..... ..... ..... @vvv
vor_v 0111 00010010 01101 ..... ..... ..... @vvv
vxor_v 0111 00010010 01110 ..... ..... ..... @vvv
vnor_v 0111 00010010 01111 ..... ..... ..... @vvv
vandn_v 0111 00010010 10000 ..... ..... ..... @vvv
vorn_v 0111 00010010 10001 ..... ..... ..... @vvv
vandi_b 0111 00111101 00 ........ ..... ..... @vv_ui8
vori_b 0111 00111101 01 ........ ..... ..... @vv_ui8
vxori_b 0111 00111101 10 ........ ..... ..... @vv_ui8
vnori_b 0111 00111101 11 ........ ..... ..... @vv_ui8
target/loongarch: Implement vsll vsrl vsra vrotr This patch includes: - VSLL[I].{B/H/W/D}; - VSRL[I].{B/H/W/D}; - VSRA[I].{B/H/W/D}; - VROTR[I].{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-23-gaosong@loongson.cn>
2023-05-04 15:27:48 +03:00
vsll_b 0111 00001110 10000 ..... ..... ..... @vvv
vsll_h 0111 00001110 10001 ..... ..... ..... @vvv
vsll_w 0111 00001110 10010 ..... ..... ..... @vvv
vsll_d 0111 00001110 10011 ..... ..... ..... @vvv
vslli_b 0111 00110010 11000 01 ... ..... ..... @vv_ui3
vslli_h 0111 00110010 11000 1 .... ..... ..... @vv_ui4
vslli_w 0111 00110010 11001 ..... ..... ..... @vv_ui5
vslli_d 0111 00110010 1101 ...... ..... ..... @vv_ui6
vsrl_b 0111 00001110 10100 ..... ..... ..... @vvv
vsrl_h 0111 00001110 10101 ..... ..... ..... @vvv
vsrl_w 0111 00001110 10110 ..... ..... ..... @vvv
vsrl_d 0111 00001110 10111 ..... ..... ..... @vvv
vsrli_b 0111 00110011 00000 01 ... ..... ..... @vv_ui3
vsrli_h 0111 00110011 00000 1 .... ..... ..... @vv_ui4
vsrli_w 0111 00110011 00001 ..... ..... ..... @vv_ui5
vsrli_d 0111 00110011 0001 ...... ..... ..... @vv_ui6
vsra_b 0111 00001110 11000 ..... ..... ..... @vvv
vsra_h 0111 00001110 11001 ..... ..... ..... @vvv
vsra_w 0111 00001110 11010 ..... ..... ..... @vvv
vsra_d 0111 00001110 11011 ..... ..... ..... @vvv
vsrai_b 0111 00110011 01000 01 ... ..... ..... @vv_ui3
vsrai_h 0111 00110011 01000 1 .... ..... ..... @vv_ui4
vsrai_w 0111 00110011 01001 ..... ..... ..... @vv_ui5
vsrai_d 0111 00110011 0101 ...... ..... ..... @vv_ui6
vrotr_b 0111 00001110 11100 ..... ..... ..... @vvv
vrotr_h 0111 00001110 11101 ..... ..... ..... @vvv
vrotr_w 0111 00001110 11110 ..... ..... ..... @vvv
vrotr_d 0111 00001110 11111 ..... ..... ..... @vvv
vrotri_b 0111 00101010 00000 01 ... ..... ..... @vv_ui3
vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4
vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5
vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6
target/loongarch: Implement vsllwil vextl This patch includes: - VSLLWIL.{H.B/W.H/D.W}; - VSLLWIL.{HU.BU/WU.HU/DU.WU}; - VEXTL.Q.D, VEXTL.QU.DU. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-24-gaosong@loongson.cn>
2023-05-04 15:27:49 +03:00
vsllwil_h_b 0111 00110000 10000 01 ... ..... ..... @vv_ui3
vsllwil_w_h 0111 00110000 10000 1 .... ..... ..... @vv_ui4
vsllwil_d_w 0111 00110000 10001 ..... ..... ..... @vv_ui5
vextl_q_d 0111 00110000 10010 00000 ..... ..... @vv
vsllwil_hu_bu 0111 00110000 11000 01 ... ..... ..... @vv_ui3
vsllwil_wu_hu 0111 00110000 11000 1 .... ..... ..... @vv_ui4
vsllwil_du_wu 0111 00110000 11001 ..... ..... ..... @vv_ui5
vextl_qu_du 0111 00110000 11010 00000 ..... ..... @vv
target/loongarch: Implement vsrlr vsrar This patch includes: - VSRLR[I].{B/H/W/D}; - VSRAR[I].{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-25-gaosong@loongson.cn>
2023-05-04 15:27:50 +03:00
vsrlr_b 0111 00001111 00000 ..... ..... ..... @vvv
vsrlr_h 0111 00001111 00001 ..... ..... ..... @vvv
vsrlr_w 0111 00001111 00010 ..... ..... ..... @vvv
vsrlr_d 0111 00001111 00011 ..... ..... ..... @vvv
vsrlri_b 0111 00101010 01000 01 ... ..... ..... @vv_ui3
vsrlri_h 0111 00101010 01000 1 .... ..... ..... @vv_ui4
vsrlri_w 0111 00101010 01001 ..... ..... ..... @vv_ui5
vsrlri_d 0111 00101010 0101 ...... ..... ..... @vv_ui6
vsrar_b 0111 00001111 00100 ..... ..... ..... @vvv
vsrar_h 0111 00001111 00101 ..... ..... ..... @vvv
vsrar_w 0111 00001111 00110 ..... ..... ..... @vvv
vsrar_d 0111 00001111 00111 ..... ..... ..... @vvv
vsrari_b 0111 00101010 10000 01 ... ..... ..... @vv_ui3
vsrari_h 0111 00101010 10000 1 .... ..... ..... @vv_ui4
vsrari_w 0111 00101010 10001 ..... ..... ..... @vv_ui5
vsrari_d 0111 00101010 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement vsrln vsran This patch includes: - VSRLN.{B.H/H.W/W.D}; - VSRAN.{B.H/H.W/W.D}; - VSRLNI.{B.H/H.W/W.D/D.Q}; - VSRANI.{B.H/H.W/W.D/D.Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-26-gaosong@loongson.cn>
2023-05-04 15:27:51 +03:00
vsrln_b_h 0111 00001111 01001 ..... ..... ..... @vvv
vsrln_h_w 0111 00001111 01010 ..... ..... ..... @vvv
vsrln_w_d 0111 00001111 01011 ..... ..... ..... @vvv
vsran_b_h 0111 00001111 01101 ..... ..... ..... @vvv
vsran_h_w 0111 00001111 01110 ..... ..... ..... @vvv
vsran_w_d 0111 00001111 01111 ..... ..... ..... @vvv
vsrlni_b_h 0111 00110100 00000 1 .... ..... ..... @vv_ui4
vsrlni_h_w 0111 00110100 00001 ..... ..... ..... @vv_ui5
vsrlni_w_d 0111 00110100 0001 ...... ..... ..... @vv_ui6
vsrlni_d_q 0111 00110100 001 ....... ..... ..... @vv_ui7
vsrani_b_h 0111 00110101 10000 1 .... ..... ..... @vv_ui4
vsrani_h_w 0111 00110101 10001 ..... ..... ..... @vv_ui5
vsrani_w_d 0111 00110101 1001 ...... ..... ..... @vv_ui6
vsrani_d_q 0111 00110101 101 ....... ..... ..... @vv_ui7
target/loongarch: Implement vsrlrn vsrarn This patch includes: - VSRLRN.{B.H/H.W/W.D}; - VSRARN.{B.H/H.W/W.D}; - VSRLRNI.{B.H/H.W/W.D/D.Q}; - VSRARNI.{B.H/H.W/W.D/D.Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-27-gaosong@loongson.cn>
2023-05-04 15:27:52 +03:00
vsrlrn_b_h 0111 00001111 10001 ..... ..... ..... @vvv
vsrlrn_h_w 0111 00001111 10010 ..... ..... ..... @vvv
vsrlrn_w_d 0111 00001111 10011 ..... ..... ..... @vvv
vsrarn_b_h 0111 00001111 10101 ..... ..... ..... @vvv
vsrarn_h_w 0111 00001111 10110 ..... ..... ..... @vvv
vsrarn_w_d 0111 00001111 10111 ..... ..... ..... @vvv
vsrlrni_b_h 0111 00110100 01000 1 .... ..... ..... @vv_ui4
vsrlrni_h_w 0111 00110100 01001 ..... ..... ..... @vv_ui5
vsrlrni_w_d 0111 00110100 0101 ...... ..... ..... @vv_ui6
vsrlrni_d_q 0111 00110100 011 ....... ..... ..... @vv_ui7
vsrarni_b_h 0111 00110101 11000 1 .... ..... ..... @vv_ui4
vsrarni_h_w 0111 00110101 11001 ..... ..... ..... @vv_ui5
vsrarni_w_d 0111 00110101 1101 ...... ..... ..... @vv_ui6
vsrarni_d_q 0111 00110101 111 ....... ..... ..... @vv_ui7
target/loongarch: Implement vssrln vssran This patch includes: - VSSRLN.{B.H/H.W/W.D}; - VSSRAN.{B.H/H.W/W.D}; - VSSRLN.{BU.H/HU.W/WU.D}; - VSSRAN.{BU.H/HU.W/WU.D}; - VSSRLNI.{B.H/H.W/W.D/D.Q}; - VSSRANI.{B.H/H.W/W.D/D.Q}; - VSSRLNI.{BU.H/HU.W/WU.D/DU.Q}; - VSSRANI.{BU.H/HU.W/WU.D/DU.Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-28-gaosong@loongson.cn>
2023-05-04 15:27:53 +03:00
vssrln_b_h 0111 00001111 11001 ..... ..... ..... @vvv
vssrln_h_w 0111 00001111 11010 ..... ..... ..... @vvv
vssrln_w_d 0111 00001111 11011 ..... ..... ..... @vvv
vssran_b_h 0111 00001111 11101 ..... ..... ..... @vvv
vssran_h_w 0111 00001111 11110 ..... ..... ..... @vvv
vssran_w_d 0111 00001111 11111 ..... ..... ..... @vvv
vssrln_bu_h 0111 00010000 01001 ..... ..... ..... @vvv
vssrln_hu_w 0111 00010000 01010 ..... ..... ..... @vvv
vssrln_wu_d 0111 00010000 01011 ..... ..... ..... @vvv
vssran_bu_h 0111 00010000 01101 ..... ..... ..... @vvv
vssran_hu_w 0111 00010000 01110 ..... ..... ..... @vvv
vssran_wu_d 0111 00010000 01111 ..... ..... ..... @vvv
vssrlni_b_h 0111 00110100 10000 1 .... ..... ..... @vv_ui4
vssrlni_h_w 0111 00110100 10001 ..... ..... ..... @vv_ui5
vssrlni_w_d 0111 00110100 1001 ...... ..... ..... @vv_ui6
vssrlni_d_q 0111 00110100 101 ....... ..... ..... @vv_ui7
vssrani_b_h 0111 00110110 00000 1 .... ..... ..... @vv_ui4
vssrani_h_w 0111 00110110 00001 ..... ..... ..... @vv_ui5
vssrani_w_d 0111 00110110 0001 ...... ..... ..... @vv_ui6
vssrani_d_q 0111 00110110 001 ....... ..... ..... @vv_ui7
vssrlni_bu_h 0111 00110100 11000 1 .... ..... ..... @vv_ui4
vssrlni_hu_w 0111 00110100 11001 ..... ..... ..... @vv_ui5
vssrlni_wu_d 0111 00110100 1101 ...... ..... ..... @vv_ui6
vssrlni_du_q 0111 00110100 111 ....... ..... ..... @vv_ui7
vssrani_bu_h 0111 00110110 01000 1 .... ..... ..... @vv_ui4
vssrani_hu_w 0111 00110110 01001 ..... ..... ..... @vv_ui5
vssrani_wu_d 0111 00110110 0101 ...... ..... ..... @vv_ui6
vssrani_du_q 0111 00110110 011 ....... ..... ..... @vv_ui7
target/loongarch: Implement vssrlrn vssrarn This patch includes: - VSSRLRN.{B.H/H.W/W.D}; - VSSRARN.{B.H/H.W/W.D}; - VSSRLRN.{BU.H/HU.W/WU.D}; - VSSRARN.{BU.H/HU.W/WU.D}; - VSSRLRNI.{B.H/H.W/W.D/D.Q}; - VSSRARNI.{B.H/H.W/W.D/D.Q}; - VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q}; - VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-29-gaosong@loongson.cn>
2023-05-04 15:27:54 +03:00
vssrlrn_b_h 0111 00010000 00001 ..... ..... ..... @vvv
vssrlrn_h_w 0111 00010000 00010 ..... ..... ..... @vvv
vssrlrn_w_d 0111 00010000 00011 ..... ..... ..... @vvv
vssrarn_b_h 0111 00010000 00101 ..... ..... ..... @vvv
vssrarn_h_w 0111 00010000 00110 ..... ..... ..... @vvv
vssrarn_w_d 0111 00010000 00111 ..... ..... ..... @vvv
vssrlrn_bu_h 0111 00010000 10001 ..... ..... ..... @vvv
vssrlrn_hu_w 0111 00010000 10010 ..... ..... ..... @vvv
vssrlrn_wu_d 0111 00010000 10011 ..... ..... ..... @vvv
vssrarn_bu_h 0111 00010000 10101 ..... ..... ..... @vvv
vssrarn_hu_w 0111 00010000 10110 ..... ..... ..... @vvv
vssrarn_wu_d 0111 00010000 10111 ..... ..... ..... @vvv
vssrlrni_b_h 0111 00110101 00000 1 .... ..... ..... @vv_ui4
vssrlrni_h_w 0111 00110101 00001 ..... ..... ..... @vv_ui5
vssrlrni_w_d 0111 00110101 0001 ...... ..... ..... @vv_ui6
vssrlrni_d_q 0111 00110101 001 ....... ..... ..... @vv_ui7
vssrarni_b_h 0111 00110110 10000 1 .... ..... ..... @vv_ui4
vssrarni_h_w 0111 00110110 10001 ..... ..... ..... @vv_ui5
vssrarni_w_d 0111 00110110 1001 ...... ..... ..... @vv_ui6
vssrarni_d_q 0111 00110110 101 ....... ..... ..... @vv_ui7
vssrlrni_bu_h 0111 00110101 01000 1 .... ..... ..... @vv_ui4
vssrlrni_hu_w 0111 00110101 01001 ..... ..... ..... @vv_ui5
vssrlrni_wu_d 0111 00110101 0101 ...... ..... ..... @vv_ui6
vssrlrni_du_q 0111 00110101 011 ....... ..... ..... @vv_ui7
vssrarni_bu_h 0111 00110110 11000 1 .... ..... ..... @vv_ui4
vssrarni_hu_w 0111 00110110 11001 ..... ..... ..... @vv_ui5
vssrarni_wu_d 0111 00110110 1101 ...... ..... ..... @vv_ui6
vssrarni_du_q 0111 00110110 111 ....... ..... ..... @vv_ui7
target/loongarch: Implement vclo vclz This patch includes: - VCLO.{B/H/W/D}; - VCLZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-30-gaosong@loongson.cn>
2023-05-04 15:27:55 +03:00
vclo_b 0111 00101001 11000 00000 ..... ..... @vv
vclo_h 0111 00101001 11000 00001 ..... ..... @vv
vclo_w 0111 00101001 11000 00010 ..... ..... @vv
vclo_d 0111 00101001 11000 00011 ..... ..... @vv
vclz_b 0111 00101001 11000 00100 ..... ..... @vv
vclz_h 0111 00101001 11000 00101 ..... ..... @vv
vclz_w 0111 00101001 11000 00110 ..... ..... @vv
vclz_d 0111 00101001 11000 00111 ..... ..... @vv
target/loongarch: Implement vpcnt This patch includes: - VPCNT.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-31-gaosong@loongson.cn>
2023-05-04 15:27:56 +03:00
vpcnt_b 0111 00101001 11000 01000 ..... ..... @vv
vpcnt_h 0111 00101001 11000 01001 ..... ..... @vv
vpcnt_w 0111 00101001 11000 01010 ..... ..... @vv
vpcnt_d 0111 00101001 11000 01011 ..... ..... @vv
target/loongarch: Implement vbitclr vbitset vbitrev This patch includes: - VBITCLR[I].{B/H/W/D}; - VBITSET[I].{B/H/W/D}; - VBITREV[I].{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-32-gaosong@loongson.cn>
2023-05-04 15:27:57 +03:00
vbitclr_b 0111 00010000 11000 ..... ..... ..... @vvv
vbitclr_h 0111 00010000 11001 ..... ..... ..... @vvv
vbitclr_w 0111 00010000 11010 ..... ..... ..... @vvv
vbitclr_d 0111 00010000 11011 ..... ..... ..... @vvv
vbitclri_b 0111 00110001 00000 01 ... ..... ..... @vv_ui3
vbitclri_h 0111 00110001 00000 1 .... ..... ..... @vv_ui4
vbitclri_w 0111 00110001 00001 ..... ..... ..... @vv_ui5
vbitclri_d 0111 00110001 0001 ...... ..... ..... @vv_ui6
vbitset_b 0111 00010000 11100 ..... ..... ..... @vvv
vbitset_h 0111 00010000 11101 ..... ..... ..... @vvv
vbitset_w 0111 00010000 11110 ..... ..... ..... @vvv
vbitset_d 0111 00010000 11111 ..... ..... ..... @vvv
vbitseti_b 0111 00110001 01000 01 ... ..... ..... @vv_ui3
vbitseti_h 0111 00110001 01000 1 .... ..... ..... @vv_ui4
vbitseti_w 0111 00110001 01001 ..... ..... ..... @vv_ui5
vbitseti_d 0111 00110001 0101 ...... ..... ..... @vv_ui6
vbitrev_b 0111 00010001 00000 ..... ..... ..... @vvv
vbitrev_h 0111 00010001 00001 ..... ..... ..... @vvv
vbitrev_w 0111 00010001 00010 ..... ..... ..... @vvv
vbitrev_d 0111 00010001 00011 ..... ..... ..... @vvv
vbitrevi_b 0111 00110001 10000 01 ... ..... ..... @vv_ui3
vbitrevi_h 0111 00110001 10000 1 .... ..... ..... @vv_ui4
vbitrevi_w 0111 00110001 10001 ..... ..... ..... @vv_ui5
vbitrevi_d 0111 00110001 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement vfrstp This patch includes: - VFRSTP[I].{B/H}. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-33-gaosong@loongson.cn>
2023-05-04 15:27:58 +03:00
vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv
vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv
vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5
vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5
target/loongarch: Implement LSX fpu arith instructions This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
2023-05-04 15:27:59 +03:00
vfadd_s 0111 00010011 00001 ..... ..... ..... @vvv
vfadd_d 0111 00010011 00010 ..... ..... ..... @vvv
vfsub_s 0111 00010011 00101 ..... ..... ..... @vvv
vfsub_d 0111 00010011 00110 ..... ..... ..... @vvv
vfmul_s 0111 00010011 10001 ..... ..... ..... @vvv
vfmul_d 0111 00010011 10010 ..... ..... ..... @vvv
vfdiv_s 0111 00010011 10101 ..... ..... ..... @vvv
vfdiv_d 0111 00010011 10110 ..... ..... ..... @vvv
vfmadd_s 0000 10010001 ..... ..... ..... ..... @vvvv
vfmadd_d 0000 10010010 ..... ..... ..... ..... @vvvv
vfmsub_s 0000 10010101 ..... ..... ..... ..... @vvvv
vfmsub_d 0000 10010110 ..... ..... ..... ..... @vvvv
vfnmadd_s 0000 10011001 ..... ..... ..... ..... @vvvv
vfnmadd_d 0000 10011010 ..... ..... ..... ..... @vvvv
vfnmsub_s 0000 10011101 ..... ..... ..... ..... @vvvv
vfnmsub_d 0000 10011110 ..... ..... ..... ..... @vvvv
vfmax_s 0111 00010011 11001 ..... ..... ..... @vvv
vfmax_d 0111 00010011 11010 ..... ..... ..... @vvv
vfmin_s 0111 00010011 11101 ..... ..... ..... @vvv
vfmin_d 0111 00010011 11110 ..... ..... ..... @vvv
vfmaxa_s 0111 00010100 00001 ..... ..... ..... @vvv
vfmaxa_d 0111 00010100 00010 ..... ..... ..... @vvv
vfmina_s 0111 00010100 00101 ..... ..... ..... @vvv
vfmina_d 0111 00010100 00110 ..... ..... ..... @vvv
vflogb_s 0111 00101001 11001 10001 ..... ..... @vv
vflogb_d 0111 00101001 11001 10010 ..... ..... @vv
vfclass_s 0111 00101001 11001 10101 ..... ..... @vv
vfclass_d 0111 00101001 11001 10110 ..... ..... @vv
vfsqrt_s 0111 00101001 11001 11001 ..... ..... @vv
vfsqrt_d 0111 00101001 11001 11010 ..... ..... @vv
vfrecip_s 0111 00101001 11001 11101 ..... ..... @vv
vfrecip_d 0111 00101001 11001 11110 ..... ..... @vv
vfrsqrt_s 0111 00101001 11010 00001 ..... ..... @vv
vfrsqrt_d 0111 00101001 11010 00010 ..... ..... @vv
target/loongarch: Implement LSX fpu fcvt instructions This patch includes: - VFCVT{L/H}.{S.H/D.S}; - VFCVT.{H.S/S.D}; - VFRINT[{RNE/RZ/RP/RM}].{S/D}; - VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - VFTINT[RZ].{WU.S/LU.D}; - VFTINT[{RNE/RZ/RP/RM}].W.D; - VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - VFFINT.{S.W/D.L}[U]; - VFFINT.S.L, VFFINT{L/H}.D.W. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-35-gaosong@loongson.cn>
2023-05-04 15:28:00 +03:00
vfcvtl_s_h 0111 00101001 11011 11010 ..... ..... @vv
vfcvth_s_h 0111 00101001 11011 11011 ..... ..... @vv
vfcvtl_d_s 0111 00101001 11011 11100 ..... ..... @vv
vfcvth_d_s 0111 00101001 11011 11101 ..... ..... @vv
vfcvt_h_s 0111 00010100 01100 ..... ..... ..... @vvv
vfcvt_s_d 0111 00010100 01101 ..... ..... ..... @vvv
vfrint_s 0111 00101001 11010 01101 ..... ..... @vv
vfrint_d 0111 00101001 11010 01110 ..... ..... @vv
vfrintrm_s 0111 00101001 11010 10001 ..... ..... @vv
vfrintrm_d 0111 00101001 11010 10010 ..... ..... @vv
vfrintrp_s 0111 00101001 11010 10101 ..... ..... @vv
vfrintrp_d 0111 00101001 11010 10110 ..... ..... @vv
vfrintrz_s 0111 00101001 11010 11001 ..... ..... @vv
vfrintrz_d 0111 00101001 11010 11010 ..... ..... @vv
vfrintrne_s 0111 00101001 11010 11101 ..... ..... @vv
vfrintrne_d 0111 00101001 11010 11110 ..... ..... @vv
vftint_w_s 0111 00101001 11100 01100 ..... ..... @vv
vftint_l_d 0111 00101001 11100 01101 ..... ..... @vv
vftintrm_w_s 0111 00101001 11100 01110 ..... ..... @vv
vftintrm_l_d 0111 00101001 11100 01111 ..... ..... @vv
vftintrp_w_s 0111 00101001 11100 10000 ..... ..... @vv
vftintrp_l_d 0111 00101001 11100 10001 ..... ..... @vv
vftintrz_w_s 0111 00101001 11100 10010 ..... ..... @vv
vftintrz_l_d 0111 00101001 11100 10011 ..... ..... @vv
vftintrne_w_s 0111 00101001 11100 10100 ..... ..... @vv
vftintrne_l_d 0111 00101001 11100 10101 ..... ..... @vv
vftint_wu_s 0111 00101001 11100 10110 ..... ..... @vv
vftint_lu_d 0111 00101001 11100 10111 ..... ..... @vv
vftintrz_wu_s 0111 00101001 11100 11100 ..... ..... @vv
vftintrz_lu_d 0111 00101001 11100 11101 ..... ..... @vv
vftint_w_d 0111 00010100 10011 ..... ..... ..... @vvv
vftintrm_w_d 0111 00010100 10100 ..... ..... ..... @vvv
vftintrp_w_d 0111 00010100 10101 ..... ..... ..... @vvv
vftintrz_w_d 0111 00010100 10110 ..... ..... ..... @vvv
vftintrne_w_d 0111 00010100 10111 ..... ..... ..... @vvv
vftintl_l_s 0111 00101001 11101 00000 ..... ..... @vv
vftinth_l_s 0111 00101001 11101 00001 ..... ..... @vv
vftintrml_l_s 0111 00101001 11101 00010 ..... ..... @vv
vftintrmh_l_s 0111 00101001 11101 00011 ..... ..... @vv
vftintrpl_l_s 0111 00101001 11101 00100 ..... ..... @vv
vftintrph_l_s 0111 00101001 11101 00101 ..... ..... @vv
vftintrzl_l_s 0111 00101001 11101 00110 ..... ..... @vv
vftintrzh_l_s 0111 00101001 11101 00111 ..... ..... @vv
vftintrnel_l_s 0111 00101001 11101 01000 ..... ..... @vv
vftintrneh_l_s 0111 00101001 11101 01001 ..... ..... @vv
vffint_s_w 0111 00101001 11100 00000 ..... ..... @vv
vffint_s_wu 0111 00101001 11100 00001 ..... ..... @vv
vffint_d_l 0111 00101001 11100 00010 ..... ..... @vv
vffint_d_lu 0111 00101001 11100 00011 ..... ..... @vv
vffintl_d_w 0111 00101001 11100 00100 ..... ..... @vv
vffinth_d_w 0111 00101001 11100 00101 ..... ..... @vv
vffint_s_l 0111 00010100 10000 ..... ..... ..... @vvv
target/loongarch: Implement vseq vsle vslt This patch includes: - VSEQ[I].{B/H/W/D}; - VSLE[I].{B/H/W/D}[U]; - VSLT[I].{B/H/W/D/}[U]. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-36-gaosong@loongson.cn>
2023-05-04 15:28:01 +03:00
vseq_b 0111 00000000 00000 ..... ..... ..... @vvv
vseq_h 0111 00000000 00001 ..... ..... ..... @vvv
vseq_w 0111 00000000 00010 ..... ..... ..... @vvv
vseq_d 0111 00000000 00011 ..... ..... ..... @vvv
vseqi_b 0111 00101000 00000 ..... ..... ..... @vv_i5
vseqi_h 0111 00101000 00001 ..... ..... ..... @vv_i5
vseqi_w 0111 00101000 00010 ..... ..... ..... @vv_i5
vseqi_d 0111 00101000 00011 ..... ..... ..... @vv_i5
vsle_b 0111 00000000 00100 ..... ..... ..... @vvv
vsle_h 0111 00000000 00101 ..... ..... ..... @vvv
vsle_w 0111 00000000 00110 ..... ..... ..... @vvv
vsle_d 0111 00000000 00111 ..... ..... ..... @vvv
vslei_b 0111 00101000 00100 ..... ..... ..... @vv_i5
vslei_h 0111 00101000 00101 ..... ..... ..... @vv_i5
vslei_w 0111 00101000 00110 ..... ..... ..... @vv_i5
vslei_d 0111 00101000 00111 ..... ..... ..... @vv_i5
vsle_bu 0111 00000000 01000 ..... ..... ..... @vvv
vsle_hu 0111 00000000 01001 ..... ..... ..... @vvv
vsle_wu 0111 00000000 01010 ..... ..... ..... @vvv
vsle_du 0111 00000000 01011 ..... ..... ..... @vvv
vslei_bu 0111 00101000 01000 ..... ..... ..... @vv_ui5
vslei_hu 0111 00101000 01001 ..... ..... ..... @vv_ui5
vslei_wu 0111 00101000 01010 ..... ..... ..... @vv_ui5
vslei_du 0111 00101000 01011 ..... ..... ..... @vv_ui5
vslt_b 0111 00000000 01100 ..... ..... ..... @vvv
vslt_h 0111 00000000 01101 ..... ..... ..... @vvv
vslt_w 0111 00000000 01110 ..... ..... ..... @vvv
vslt_d 0111 00000000 01111 ..... ..... ..... @vvv
vslti_b 0111 00101000 01100 ..... ..... ..... @vv_i5
vslti_h 0111 00101000 01101 ..... ..... ..... @vv_i5
vslti_w 0111 00101000 01110 ..... ..... ..... @vv_i5
vslti_d 0111 00101000 01111 ..... ..... ..... @vv_i5
vslt_bu 0111 00000000 10000 ..... ..... ..... @vvv
vslt_hu 0111 00000000 10001 ..... ..... ..... @vvv
vslt_wu 0111 00000000 10010 ..... ..... ..... @vvv
vslt_du 0111 00000000 10011 ..... ..... ..... @vvv
vslti_bu 0111 00101000 10000 ..... ..... ..... @vv_ui5
vslti_hu 0111 00101000 10001 ..... ..... ..... @vv_ui5
vslti_wu 0111 00101000 10010 ..... ..... ..... @vv_ui5
vslti_du 0111 00101000 10011 ..... ..... ..... @vv_ui5
target/loongarch: Implement vfcmp This patch includes: - VFCMP.cond.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-37-gaosong@loongson.cn>
2023-05-04 15:28:02 +03:00
vfcmp_cond_s 0000 11000101 ..... ..... ..... ..... @vvv_fcond
vfcmp_cond_d 0000 11000110 ..... ..... ..... ..... @vvv_fcond
target/loongarch: Implement vbitsel vset This patch includes: - VBITSEL.V; - VBITSELI.B; - VSET{EQZ/NEZ}.V; - VSETANYEQZ.{B/H/W/D}; - VSETALLNEZ.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
2023-05-04 15:28:03 +03:00
vbitsel_v 0000 11010001 ..... ..... ..... ..... @vvvv
vbitseli_b 0111 00111100 01 ........ ..... ..... @vv_ui8
vseteqz_v 0111 00101001 11001 00110 ..... 00 ... @cv
vsetnez_v 0111 00101001 11001 00111 ..... 00 ... @cv
vsetanyeqz_b 0111 00101001 11001 01000 ..... 00 ... @cv
vsetanyeqz_h 0111 00101001 11001 01001 ..... 00 ... @cv
vsetanyeqz_w 0111 00101001 11001 01010 ..... 00 ... @cv
vsetanyeqz_d 0111 00101001 11001 01011 ..... 00 ... @cv
vsetallnez_b 0111 00101001 11001 01100 ..... 00 ... @cv
vsetallnez_h 0111 00101001 11001 01101 ..... 00 ... @cv
vsetallnez_w 0111 00101001 11001 01110 ..... 00 ... @cv
vsetallnez_d 0111 00101001 11001 01111 ..... 00 ... @cv
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr This patch includes: - VINSGR2VR.{B/H/W/D}; - VPICKVE2GR.{B/H/W/D}[U]; - VREPLGR2VR.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
2023-05-04 15:28:04 +03:00
vinsgr2vr_b 0111 00101110 10111 0 .... ..... ..... @vr_ui4
vinsgr2vr_h 0111 00101110 10111 10 ... ..... ..... @vr_ui3
vinsgr2vr_w 0111 00101110 10111 110 .. ..... ..... @vr_ui2
vinsgr2vr_d 0111 00101110 10111 1110 . ..... ..... @vr_ui1
vpickve2gr_b 0111 00101110 11111 0 .... ..... ..... @rv_ui4
vpickve2gr_h 0111 00101110 11111 10 ... ..... ..... @rv_ui3
vpickve2gr_w 0111 00101110 11111 110 .. ..... ..... @rv_ui2
vpickve2gr_d 0111 00101110 11111 1110 . ..... ..... @rv_ui1
vpickve2gr_bu 0111 00101111 00111 0 .... ..... ..... @rv_ui4
vpickve2gr_hu 0111 00101111 00111 10 ... ..... ..... @rv_ui3
vpickve2gr_wu 0111 00101111 00111 110 .. ..... ..... @rv_ui2
vpickve2gr_du 0111 00101111 00111 1110 . ..... ..... @rv_ui1
vreplgr2vr_b 0111 00101001 11110 00000 ..... ..... @vr
vreplgr2vr_h 0111 00101001 11110 00001 ..... ..... @vr
vreplgr2vr_w 0111 00101001 11110 00010 ..... ..... @vr
vreplgr2vr_d 0111 00101001 11110 00011 ..... ..... @vr
target/loongarch: Implement vreplve vpack vpick This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
2023-05-04 15:28:05 +03:00
vreplve_b 0111 00010010 00100 ..... ..... ..... @vvr
vreplve_h 0111 00010010 00101 ..... ..... ..... @vvr
vreplve_w 0111 00010010 00110 ..... ..... ..... @vvr
vreplve_d 0111 00010010 00111 ..... ..... ..... @vvr
vreplvei_b 0111 00101111 01111 0 .... ..... ..... @vv_ui4
vreplvei_h 0111 00101111 01111 10 ... ..... ..... @vv_ui3
vreplvei_w 0111 00101111 01111 110 .. ..... ..... @vv_ui2
vreplvei_d 0111 00101111 01111 1110 . ..... ..... @vv_ui1
vbsll_v 0111 00101000 11100 ..... ..... ..... @vv_ui5
vbsrl_v 0111 00101000 11101 ..... ..... ..... @vv_ui5
vpackev_b 0111 00010001 01100 ..... ..... ..... @vvv
vpackev_h 0111 00010001 01101 ..... ..... ..... @vvv
vpackev_w 0111 00010001 01110 ..... ..... ..... @vvv
vpackev_d 0111 00010001 01111 ..... ..... ..... @vvv
vpackod_b 0111 00010001 10000 ..... ..... ..... @vvv
vpackod_h 0111 00010001 10001 ..... ..... ..... @vvv
vpackod_w 0111 00010001 10010 ..... ..... ..... @vvv
vpackod_d 0111 00010001 10011 ..... ..... ..... @vvv
vpickev_b 0111 00010001 11100 ..... ..... ..... @vvv
vpickev_h 0111 00010001 11101 ..... ..... ..... @vvv
vpickev_w 0111 00010001 11110 ..... ..... ..... @vvv
vpickev_d 0111 00010001 11111 ..... ..... ..... @vvv
vpickod_b 0111 00010010 00000 ..... ..... ..... @vvv
vpickod_h 0111 00010010 00001 ..... ..... ..... @vvv
vpickod_w 0111 00010010 00010 ..... ..... ..... @vvv
vpickod_d 0111 00010010 00011 ..... ..... ..... @vvv
target/loongarch: Implement vilvl vilvh vextrins vshuf This patch includes: - VILV{L/H}.{B/H/W/D}; - VSHUF.{B/H/W/D}; - VSHUF4I.{B/H/W/D}; - VPERMI.W; - VEXTRINS.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-41-gaosong@loongson.cn>
2023-05-04 15:28:06 +03:00
vilvl_b 0111 00010001 10100 ..... ..... ..... @vvv
vilvl_h 0111 00010001 10101 ..... ..... ..... @vvv
vilvl_w 0111 00010001 10110 ..... ..... ..... @vvv
vilvl_d 0111 00010001 10111 ..... ..... ..... @vvv
vilvh_b 0111 00010001 11000 ..... ..... ..... @vvv
vilvh_h 0111 00010001 11001 ..... ..... ..... @vvv
vilvh_w 0111 00010001 11010 ..... ..... ..... @vvv
vilvh_d 0111 00010001 11011 ..... ..... ..... @vvv
vshuf_b 0000 11010101 ..... ..... ..... ..... @vvvv
vshuf_h 0111 00010111 10101 ..... ..... ..... @vvv
vshuf_w 0111 00010111 10110 ..... ..... ..... @vvv
vshuf_d 0111 00010111 10111 ..... ..... ..... @vvv
vshuf4i_b 0111 00111001 00 ........ ..... ..... @vv_ui8
vshuf4i_h 0111 00111001 01 ........ ..... ..... @vv_ui8
vshuf4i_w 0111 00111001 10 ........ ..... ..... @vv_ui8
vshuf4i_d 0111 00111001 11 ........ ..... ..... @vv_ui8
vpermi_w 0111 00111110 01 ........ ..... ..... @vv_ui8
vextrins_d 0111 00111000 00 ........ ..... ..... @vv_ui8
vextrins_w 0111 00111000 01 ........ ..... ..... @vv_ui8
vextrins_h 0111 00111000 10 ........ ..... ..... @vv_ui8
vextrins_b 0111 00111000 11 ........ ..... ..... @vv_ui8
target/loongarch: Implement vld vst This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
2023-05-04 15:28:07 +03:00
vld 0010 110000 ............ ..... ..... @vr_i12
vst 0010 110001 ............ ..... ..... @vr_i12
vldx 0011 10000100 00000 ..... ..... ..... @vrr
vstx 0011 10000100 01000 ..... ..... ..... @vrr
vldrepl_d 0011 00000001 0 ......... ..... ..... @vr_i9
vldrepl_w 0011 00000010 .......... ..... ..... @vr_i10
vldrepl_h 0011 0000010 ........... ..... ..... @vr_i11
vldrepl_b 0011 000010 ............ ..... ..... @vr_i12
vstelm_d 0011 00010001 0 . ........ ..... ..... @vr_i8i1
vstelm_w 0011 00010010 .. ........ ..... ..... @vr_i8i2
vstelm_h 0011 0001010 ... ........ ..... ..... @vr_i8i3
vstelm_b 0011 000110 .... ........ ..... ..... @vr_i8i4
target/loongarch: Implement xvadd/xvsub This patch includes: - XVADD.{B/H/W/D/Q}; - XVSUB.{B/H/W/D/Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-15-gaosong@loongson.cn>
2023-09-14 05:26:02 +03:00
#
# LoongArch LASX instructions
#
xvadd_b 0111 01000000 10100 ..... ..... ..... @vvv
xvadd_h 0111 01000000 10101 ..... ..... ..... @vvv
xvadd_w 0111 01000000 10110 ..... ..... ..... @vvv
xvadd_d 0111 01000000 10111 ..... ..... ..... @vvv
xvadd_q 0111 01010010 11010 ..... ..... ..... @vvv
xvsub_b 0111 01000000 11000 ..... ..... ..... @vvv
xvsub_h 0111 01000000 11001 ..... ..... ..... @vvv
xvsub_w 0111 01000000 11010 ..... ..... ..... @vvv
xvsub_d 0111 01000000 11011 ..... ..... ..... @vvv
xvsub_q 0111 01010010 11011 ..... ..... ..... @vvv
target/loongarch: Implement xvreplgr2vr This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-16-gaosong@loongson.cn>
2023-09-14 05:26:03 +03:00
target/loongarch: Implement xvaddi/xvsubi This patch includes: - XVADDI.{B/H/W/D}U; - XVSUBI.{B/H/W/D}U. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-17-gaosong@loongson.cn>
2023-09-14 05:26:04 +03:00
xvaddi_bu 0111 01101000 10100 ..... ..... ..... @vv_ui5
xvaddi_hu 0111 01101000 10101 ..... ..... ..... @vv_ui5
xvaddi_wu 0111 01101000 10110 ..... ..... ..... @vv_ui5
xvaddi_du 0111 01101000 10111 ..... ..... ..... @vv_ui5
xvsubi_bu 0111 01101000 11000 ..... ..... ..... @vv_ui5
xvsubi_hu 0111 01101000 11001 ..... ..... ..... @vv_ui5
xvsubi_wu 0111 01101000 11010 ..... ..... ..... @vv_ui5
xvsubi_du 0111 01101000 11011 ..... ..... ..... @vv_ui5
target/loongarch: Implement xvneg This patch includes: - XVNEG.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-18-gaosong@loongson.cn>
2023-09-14 05:26:05 +03:00
xvneg_b 0111 01101001 11000 01100 ..... ..... @vv
xvneg_h 0111 01101001 11000 01101 ..... ..... @vv
xvneg_w 0111 01101001 11000 01110 ..... ..... @vv
xvneg_d 0111 01101001 11000 01111 ..... ..... @vv
target/loongarch: Implement xvsadd/xvssub This patch includes: - XVSADD.{B/H/W/D}[U]; - XVSSUB.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-19-gaosong@loongson.cn>
2023-09-14 05:26:06 +03:00
xvsadd_b 0111 01000100 01100 ..... ..... ..... @vvv
xvsadd_h 0111 01000100 01101 ..... ..... ..... @vvv
xvsadd_w 0111 01000100 01110 ..... ..... ..... @vvv
xvsadd_d 0111 01000100 01111 ..... ..... ..... @vvv
xvsadd_bu 0111 01000100 10100 ..... ..... ..... @vvv
xvsadd_hu 0111 01000100 10101 ..... ..... ..... @vvv
xvsadd_wu 0111 01000100 10110 ..... ..... ..... @vvv
xvsadd_du 0111 01000100 10111 ..... ..... ..... @vvv
xvssub_b 0111 01000100 10000 ..... ..... ..... @vvv
xvssub_h 0111 01000100 10001 ..... ..... ..... @vvv
xvssub_w 0111 01000100 10010 ..... ..... ..... @vvv
xvssub_d 0111 01000100 10011 ..... ..... ..... @vvv
xvssub_bu 0111 01000100 11000 ..... ..... ..... @vvv
xvssub_hu 0111 01000100 11001 ..... ..... ..... @vvv
xvssub_wu 0111 01000100 11010 ..... ..... ..... @vvv
xvssub_du 0111 01000100 11011 ..... ..... ..... @vvv
target/loongarch: Implement xvhaddw/xvhsubw This patch includes: - XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-20-gaosong@loongson.cn>
2023-09-14 05:26:07 +03:00
xvhaddw_h_b 0111 01000101 01000 ..... ..... ..... @vvv
xvhaddw_w_h 0111 01000101 01001 ..... ..... ..... @vvv
xvhaddw_d_w 0111 01000101 01010 ..... ..... ..... @vvv
xvhaddw_q_d 0111 01000101 01011 ..... ..... ..... @vvv
xvhaddw_hu_bu 0111 01000101 10000 ..... ..... ..... @vvv
xvhaddw_wu_hu 0111 01000101 10001 ..... ..... ..... @vvv
xvhaddw_du_wu 0111 01000101 10010 ..... ..... ..... @vvv
xvhaddw_qu_du 0111 01000101 10011 ..... ..... ..... @vvv
xvhsubw_h_b 0111 01000101 01100 ..... ..... ..... @vvv
xvhsubw_w_h 0111 01000101 01101 ..... ..... ..... @vvv
xvhsubw_d_w 0111 01000101 01110 ..... ..... ..... @vvv
xvhsubw_q_d 0111 01000101 01111 ..... ..... ..... @vvv
xvhsubw_hu_bu 0111 01000101 10100 ..... ..... ..... @vvv
xvhsubw_wu_hu 0111 01000101 10101 ..... ..... ..... @vvv
xvhsubw_du_wu 0111 01000101 10110 ..... ..... ..... @vvv
xvhsubw_qu_du 0111 01000101 10111 ..... ..... ..... @vvv
target/loongarch: Implement xvaddw/xvsubw This patch includes: - XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-21-gaosong@loongson.cn>
2023-09-14 05:26:08 +03:00
xvaddwev_h_b 0111 01000001 11100 ..... ..... ..... @vvv
xvaddwev_w_h 0111 01000001 11101 ..... ..... ..... @vvv
xvaddwev_d_w 0111 01000001 11110 ..... ..... ..... @vvv
xvaddwev_q_d 0111 01000001 11111 ..... ..... ..... @vvv
xvaddwod_h_b 0111 01000010 00100 ..... ..... ..... @vvv
xvaddwod_w_h 0111 01000010 00101 ..... ..... ..... @vvv
xvaddwod_d_w 0111 01000010 00110 ..... ..... ..... @vvv
xvaddwod_q_d 0111 01000010 00111 ..... ..... ..... @vvv
xvsubwev_h_b 0111 01000010 00000 ..... ..... ..... @vvv
xvsubwev_w_h 0111 01000010 00001 ..... ..... ..... @vvv
xvsubwev_d_w 0111 01000010 00010 ..... ..... ..... @vvv
xvsubwev_q_d 0111 01000010 00011 ..... ..... ..... @vvv
xvsubwod_h_b 0111 01000010 01000 ..... ..... ..... @vvv
xvsubwod_w_h 0111 01000010 01001 ..... ..... ..... @vvv
xvsubwod_d_w 0111 01000010 01010 ..... ..... ..... @vvv
xvsubwod_q_d 0111 01000010 01011 ..... ..... ..... @vvv
xvaddwev_h_bu 0111 01000010 11100 ..... ..... ..... @vvv
xvaddwev_w_hu 0111 01000010 11101 ..... ..... ..... @vvv
xvaddwev_d_wu 0111 01000010 11110 ..... ..... ..... @vvv
xvaddwev_q_du 0111 01000010 11111 ..... ..... ..... @vvv
xvaddwod_h_bu 0111 01000011 00100 ..... ..... ..... @vvv
xvaddwod_w_hu 0111 01000011 00101 ..... ..... ..... @vvv
xvaddwod_d_wu 0111 01000011 00110 ..... ..... ..... @vvv
xvaddwod_q_du 0111 01000011 00111 ..... ..... ..... @vvv
xvsubwev_h_bu 0111 01000011 00000 ..... ..... ..... @vvv
xvsubwev_w_hu 0111 01000011 00001 ..... ..... ..... @vvv
xvsubwev_d_wu 0111 01000011 00010 ..... ..... ..... @vvv
xvsubwev_q_du 0111 01000011 00011 ..... ..... ..... @vvv
xvsubwod_h_bu 0111 01000011 01000 ..... ..... ..... @vvv
xvsubwod_w_hu 0111 01000011 01001 ..... ..... ..... @vvv
xvsubwod_d_wu 0111 01000011 01010 ..... ..... ..... @vvv
xvsubwod_q_du 0111 01000011 01011 ..... ..... ..... @vvv
xvaddwev_h_bu_b 0111 01000011 11100 ..... ..... ..... @vvv
xvaddwev_w_hu_h 0111 01000011 11101 ..... ..... ..... @vvv
xvaddwev_d_wu_w 0111 01000011 11110 ..... ..... ..... @vvv
xvaddwev_q_du_d 0111 01000011 11111 ..... ..... ..... @vvv
xvaddwod_h_bu_b 0111 01000100 00000 ..... ..... ..... @vvv
xvaddwod_w_hu_h 0111 01000100 00001 ..... ..... ..... @vvv
xvaddwod_d_wu_w 0111 01000100 00010 ..... ..... ..... @vvv
xvaddwod_q_du_d 0111 01000100 00011 ..... ..... ..... @vvv
target/loongarch: Implement xavg/xvagr This patch includes: - XVAVG.{B/H/W/D/}[U]; - XVAVGR.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-22-gaosong@loongson.cn>
2023-09-14 05:26:09 +03:00
xvavg_b 0111 01000110 01000 ..... ..... ..... @vvv
xvavg_h 0111 01000110 01001 ..... ..... ..... @vvv
xvavg_w 0111 01000110 01010 ..... ..... ..... @vvv
xvavg_d 0111 01000110 01011 ..... ..... ..... @vvv
xvavg_bu 0111 01000110 01100 ..... ..... ..... @vvv
xvavg_hu 0111 01000110 01101 ..... ..... ..... @vvv
xvavg_wu 0111 01000110 01110 ..... ..... ..... @vvv
xvavg_du 0111 01000110 01111 ..... ..... ..... @vvv
xvavgr_b 0111 01000110 10000 ..... ..... ..... @vvv
xvavgr_h 0111 01000110 10001 ..... ..... ..... @vvv
xvavgr_w 0111 01000110 10010 ..... ..... ..... @vvv
xvavgr_d 0111 01000110 10011 ..... ..... ..... @vvv
xvavgr_bu 0111 01000110 10100 ..... ..... ..... @vvv
xvavgr_hu 0111 01000110 10101 ..... ..... ..... @vvv
xvavgr_wu 0111 01000110 10110 ..... ..... ..... @vvv
xvavgr_du 0111 01000110 10111 ..... ..... ..... @vvv
target/loongarch: Implement xvabsd This patch includes: - XVABSD.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-23-gaosong@loongson.cn>
2023-09-14 05:26:10 +03:00
xvabsd_b 0111 01000110 00000 ..... ..... ..... @vvv
xvabsd_h 0111 01000110 00001 ..... ..... ..... @vvv
xvabsd_w 0111 01000110 00010 ..... ..... ..... @vvv
xvabsd_d 0111 01000110 00011 ..... ..... ..... @vvv
xvabsd_bu 0111 01000110 00100 ..... ..... ..... @vvv
xvabsd_hu 0111 01000110 00101 ..... ..... ..... @vvv
xvabsd_wu 0111 01000110 00110 ..... ..... ..... @vvv
xvabsd_du 0111 01000110 00111 ..... ..... ..... @vvv
target/loongarch: Implement xvadda This patch includes: - XVADDA.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-24-gaosong@loongson.cn>
2023-09-14 05:26:11 +03:00
xvadda_b 0111 01000101 11000 ..... ..... ..... @vvv
xvadda_h 0111 01000101 11001 ..... ..... ..... @vvv
xvadda_w 0111 01000101 11010 ..... ..... ..... @vvv
xvadda_d 0111 01000101 11011 ..... ..... ..... @vvv
target/loongarch: Implement xvmax/xvmin This patch includes: - XVMAX[I].{B/H/W/D}[U]; - XVMIN[I].{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-25-gaosong@loongson.cn>
2023-09-14 05:26:12 +03:00
xvmax_b 0111 01000111 00000 ..... ..... ..... @vvv
xvmax_h 0111 01000111 00001 ..... ..... ..... @vvv
xvmax_w 0111 01000111 00010 ..... ..... ..... @vvv
xvmax_d 0111 01000111 00011 ..... ..... ..... @vvv
xvmax_bu 0111 01000111 01000 ..... ..... ..... @vvv
xvmax_hu 0111 01000111 01001 ..... ..... ..... @vvv
xvmax_wu 0111 01000111 01010 ..... ..... ..... @vvv
xvmax_du 0111 01000111 01011 ..... ..... ..... @vvv
xvmaxi_b 0111 01101001 00000 ..... ..... ..... @vv_i5
xvmaxi_h 0111 01101001 00001 ..... ..... ..... @vv_i5
xvmaxi_w 0111 01101001 00010 ..... ..... ..... @vv_i5
xvmaxi_d 0111 01101001 00011 ..... ..... ..... @vv_i5
xvmaxi_bu 0111 01101001 01000 ..... ..... ..... @vv_ui5
xvmaxi_hu 0111 01101001 01001 ..... ..... ..... @vv_ui5
xvmaxi_wu 0111 01101001 01010 ..... ..... ..... @vv_ui5
xvmaxi_du 0111 01101001 01011 ..... ..... ..... @vv_ui5
xvmin_b 0111 01000111 00100 ..... ..... ..... @vvv
xvmin_h 0111 01000111 00101 ..... ..... ..... @vvv
xvmin_w 0111 01000111 00110 ..... ..... ..... @vvv
xvmin_d 0111 01000111 00111 ..... ..... ..... @vvv
xvmin_bu 0111 01000111 01100 ..... ..... ..... @vvv
xvmin_hu 0111 01000111 01101 ..... ..... ..... @vvv
xvmin_wu 0111 01000111 01110 ..... ..... ..... @vvv
xvmin_du 0111 01000111 01111 ..... ..... ..... @vvv
xvmini_b 0111 01101001 00100 ..... ..... ..... @vv_i5
xvmini_h 0111 01101001 00101 ..... ..... ..... @vv_i5
xvmini_w 0111 01101001 00110 ..... ..... ..... @vv_i5
xvmini_d 0111 01101001 00111 ..... ..... ..... @vv_i5
xvmini_bu 0111 01101001 01100 ..... ..... ..... @vv_ui5
xvmini_hu 0111 01101001 01101 ..... ..... ..... @vv_ui5
xvmini_wu 0111 01101001 01110 ..... ..... ..... @vv_ui5
xvmini_du 0111 01101001 01111 ..... ..... ..... @vv_ui5
target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od} This patch includes: - XVMUL.{B/H/W/D}; - XVMUH.{B/H/W/D}[U]; - XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-26-gaosong@loongson.cn>
2023-09-14 05:26:13 +03:00
xvmul_b 0111 01001000 01000 ..... ..... ..... @vvv
xvmul_h 0111 01001000 01001 ..... ..... ..... @vvv
xvmul_w 0111 01001000 01010 ..... ..... ..... @vvv
xvmul_d 0111 01001000 01011 ..... ..... ..... @vvv
xvmuh_b 0111 01001000 01100 ..... ..... ..... @vvv
xvmuh_h 0111 01001000 01101 ..... ..... ..... @vvv
xvmuh_w 0111 01001000 01110 ..... ..... ..... @vvv
xvmuh_d 0111 01001000 01111 ..... ..... ..... @vvv
xvmuh_bu 0111 01001000 10000 ..... ..... ..... @vvv
xvmuh_hu 0111 01001000 10001 ..... ..... ..... @vvv
xvmuh_wu 0111 01001000 10010 ..... ..... ..... @vvv
xvmuh_du 0111 01001000 10011 ..... ..... ..... @vvv
xvmulwev_h_b 0111 01001001 00000 ..... ..... ..... @vvv
xvmulwev_w_h 0111 01001001 00001 ..... ..... ..... @vvv
xvmulwev_d_w 0111 01001001 00010 ..... ..... ..... @vvv
xvmulwev_q_d 0111 01001001 00011 ..... ..... ..... @vvv
xvmulwod_h_b 0111 01001001 00100 ..... ..... ..... @vvv
xvmulwod_w_h 0111 01001001 00101 ..... ..... ..... @vvv
xvmulwod_d_w 0111 01001001 00110 ..... ..... ..... @vvv
xvmulwod_q_d 0111 01001001 00111 ..... ..... ..... @vvv
xvmulwev_h_bu 0111 01001001 10000 ..... ..... ..... @vvv
xvmulwev_w_hu 0111 01001001 10001 ..... ..... ..... @vvv
xvmulwev_d_wu 0111 01001001 10010 ..... ..... ..... @vvv
xvmulwev_q_du 0111 01001001 10011 ..... ..... ..... @vvv
xvmulwod_h_bu 0111 01001001 10100 ..... ..... ..... @vvv
xvmulwod_w_hu 0111 01001001 10101 ..... ..... ..... @vvv
xvmulwod_d_wu 0111 01001001 10110 ..... ..... ..... @vvv
xvmulwod_q_du 0111 01001001 10111 ..... ..... ..... @vvv
xvmulwev_h_bu_b 0111 01001010 00000 ..... ..... ..... @vvv
xvmulwev_w_hu_h 0111 01001010 00001 ..... ..... ..... @vvv
xvmulwev_d_wu_w 0111 01001010 00010 ..... ..... ..... @vvv
xvmulwev_q_du_d 0111 01001010 00011 ..... ..... ..... @vvv
xvmulwod_h_bu_b 0111 01001010 00100 ..... ..... ..... @vvv
xvmulwod_w_hu_h 0111 01001010 00101 ..... ..... ..... @vvv
xvmulwod_d_wu_w 0111 01001010 00110 ..... ..... ..... @vvv
xvmulwod_q_du_d 0111 01001010 00111 ..... ..... ..... @vvv
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od} This patch includes: - XVMADD.{B/H/W/D}; - XVMSUB.{B/H/W/D}; - XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-27-gaosong@loongson.cn>
2023-09-14 05:26:14 +03:00
xvmadd_b 0111 01001010 10000 ..... ..... ..... @vvv
xvmadd_h 0111 01001010 10001 ..... ..... ..... @vvv
xvmadd_w 0111 01001010 10010 ..... ..... ..... @vvv
xvmadd_d 0111 01001010 10011 ..... ..... ..... @vvv
xvmsub_b 0111 01001010 10100 ..... ..... ..... @vvv
xvmsub_h 0111 01001010 10101 ..... ..... ..... @vvv
xvmsub_w 0111 01001010 10110 ..... ..... ..... @vvv
xvmsub_d 0111 01001010 10111 ..... ..... ..... @vvv
xvmaddwev_h_b 0111 01001010 11000 ..... ..... ..... @vvv
xvmaddwev_w_h 0111 01001010 11001 ..... ..... ..... @vvv
xvmaddwev_d_w 0111 01001010 11010 ..... ..... ..... @vvv
xvmaddwev_q_d 0111 01001010 11011 ..... ..... ..... @vvv
xvmaddwod_h_b 0111 01001010 11100 ..... ..... ..... @vvv
xvmaddwod_w_h 0111 01001010 11101 ..... ..... ..... @vvv
xvmaddwod_d_w 0111 01001010 11110 ..... ..... ..... @vvv
xvmaddwod_q_d 0111 01001010 11111 ..... ..... ..... @vvv
xvmaddwev_h_bu 0111 01001011 01000 ..... ..... ..... @vvv
xvmaddwev_w_hu 0111 01001011 01001 ..... ..... ..... @vvv
xvmaddwev_d_wu 0111 01001011 01010 ..... ..... ..... @vvv
xvmaddwev_q_du 0111 01001011 01011 ..... ..... ..... @vvv
xvmaddwod_h_bu 0111 01001011 01100 ..... ..... ..... @vvv
xvmaddwod_w_hu 0111 01001011 01101 ..... ..... ..... @vvv
xvmaddwod_d_wu 0111 01001011 01110 ..... ..... ..... @vvv
xvmaddwod_q_du 0111 01001011 01111 ..... ..... ..... @vvv
xvmaddwev_h_bu_b 0111 01001011 11000 ..... ..... ..... @vvv
xvmaddwev_w_hu_h 0111 01001011 11001 ..... ..... ..... @vvv
xvmaddwev_d_wu_w 0111 01001011 11010 ..... ..... ..... @vvv
xvmaddwev_q_du_d 0111 01001011 11011 ..... ..... ..... @vvv
xvmaddwod_h_bu_b 0111 01001011 11100 ..... ..... ..... @vvv
xvmaddwod_w_hu_h 0111 01001011 11101 ..... ..... ..... @vvv
xvmaddwod_d_wu_w 0111 01001011 11110 ..... ..... ..... @vvv
xvmaddwod_q_du_d 0111 01001011 11111 ..... ..... ..... @vvv
target/loongarch; Implement xvdiv/xvmod This patch includes: - XVDIV.{B/H/W/D}[U]; - XVMOD.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-28-gaosong@loongson.cn>
2023-09-14 05:26:15 +03:00
xvdiv_b 0111 01001110 00000 ..... ..... ..... @vvv
xvdiv_h 0111 01001110 00001 ..... ..... ..... @vvv
xvdiv_w 0111 01001110 00010 ..... ..... ..... @vvv
xvdiv_d 0111 01001110 00011 ..... ..... ..... @vvv
xvmod_b 0111 01001110 00100 ..... ..... ..... @vvv
xvmod_h 0111 01001110 00101 ..... ..... ..... @vvv
xvmod_w 0111 01001110 00110 ..... ..... ..... @vvv
xvmod_d 0111 01001110 00111 ..... ..... ..... @vvv
xvdiv_bu 0111 01001110 01000 ..... ..... ..... @vvv
xvdiv_hu 0111 01001110 01001 ..... ..... ..... @vvv
xvdiv_wu 0111 01001110 01010 ..... ..... ..... @vvv
xvdiv_du 0111 01001110 01011 ..... ..... ..... @vvv
xvmod_bu 0111 01001110 01100 ..... ..... ..... @vvv
xvmod_hu 0111 01001110 01101 ..... ..... ..... @vvv
xvmod_wu 0111 01001110 01110 ..... ..... ..... @vvv
xvmod_du 0111 01001110 01111 ..... ..... ..... @vvv
target/loongarch: Implement xvsat This patch includes: - XVSAT.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-29-gaosong@loongson.cn>
2023-09-14 05:26:16 +03:00
xvsat_b 0111 01110010 01000 01 ... ..... ..... @vv_ui3
xvsat_h 0111 01110010 01000 1 .... ..... ..... @vv_ui4
xvsat_w 0111 01110010 01001 ..... ..... ..... @vv_ui5
xvsat_d 0111 01110010 0101 ...... ..... ..... @vv_ui6
xvsat_bu 0111 01110010 10000 01 ... ..... ..... @vv_ui3
xvsat_hu 0111 01110010 10000 1 .... ..... ..... @vv_ui4
xvsat_wu 0111 01110010 10001 ..... ..... ..... @vv_ui5
xvsat_du 0111 01110010 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement xvexth This patch includes: - XVEXTH.{H.B/W.H/D.W/Q.D}; - XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-30-gaosong@loongson.cn>
2023-09-14 05:26:17 +03:00
xvexth_h_b 0111 01101001 11101 11000 ..... ..... @vv
xvexth_w_h 0111 01101001 11101 11001 ..... ..... @vv
xvexth_d_w 0111 01101001 11101 11010 ..... ..... @vv
xvexth_q_d 0111 01101001 11101 11011 ..... ..... @vv
xvexth_hu_bu 0111 01101001 11101 11100 ..... ..... @vv
xvexth_wu_hu 0111 01101001 11101 11101 ..... ..... @vv
xvexth_du_wu 0111 01101001 11101 11110 ..... ..... @vv
xvexth_qu_du 0111 01101001 11101 11111 ..... ..... @vv
target/loongarch: Implement vext2xv This patch includes: - VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU; - VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU; - VEXT2XV.D.W, VEXT2XV.DU.WU. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-31-gaosong@loongson.cn>
2023-09-14 05:26:18 +03:00
vext2xv_h_b 0111 01101001 11110 00100 ..... ..... @vv
vext2xv_w_b 0111 01101001 11110 00101 ..... ..... @vv
vext2xv_d_b 0111 01101001 11110 00110 ..... ..... @vv
vext2xv_w_h 0111 01101001 11110 00111 ..... ..... @vv
vext2xv_d_h 0111 01101001 11110 01000 ..... ..... @vv
vext2xv_d_w 0111 01101001 11110 01001 ..... ..... @vv
vext2xv_hu_bu 0111 01101001 11110 01010 ..... ..... @vv
vext2xv_wu_bu 0111 01101001 11110 01011 ..... ..... @vv
vext2xv_du_bu 0111 01101001 11110 01100 ..... ..... @vv
vext2xv_wu_hu 0111 01101001 11110 01101 ..... ..... @vv
vext2xv_du_hu 0111 01101001 11110 01110 ..... ..... @vv
vext2xv_du_wu 0111 01101001 11110 01111 ..... ..... @vv
target/loongarch: Implement xvsigncov This patch includes: - XVSIGNCOV.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-32-gaosong@loongson.cn>
2023-09-14 05:26:19 +03:00
xvsigncov_b 0111 01010010 11100 ..... ..... ..... @vvv
xvsigncov_h 0111 01010010 11101 ..... ..... ..... @vvv
xvsigncov_w 0111 01010010 11110 ..... ..... ..... @vvv
xvsigncov_d 0111 01010010 11111 ..... ..... ..... @vvv
target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz This patch includes: - XVMSKLTZ.{B/H/W/D}; - XVMSKGEZ.B; - XVMSKNZ.B. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-33-gaosong@loongson.cn>
2023-09-14 05:26:20 +03:00
xvmskltz_b 0111 01101001 11000 10000 ..... ..... @vv
xvmskltz_h 0111 01101001 11000 10001 ..... ..... @vv
xvmskltz_w 0111 01101001 11000 10010 ..... ..... @vv
xvmskltz_d 0111 01101001 11000 10011 ..... ..... @vv
xvmskgez_b 0111 01101001 11000 10100 ..... ..... @vv
xvmsknz_b 0111 01101001 11000 11000 ..... ..... @vv
target/loongarch: Implement xvldi This patch includes: - XVLDI. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-34-gaosong@loongson.cn>
2023-09-14 05:26:21 +03:00
xvldi 0111 01111110 00 ............. ..... @v_i13
target/loongarch: Implement LASX logic instructions This patch includes: - XV{AND/OR/XOR/NOR/ANDN/ORN}.V; - XV{AND/OR/XOR/NOR}I.B. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-35-gaosong@loongson.cn>
2023-09-14 05:26:22 +03:00
xvand_v 0111 01010010 01100 ..... ..... ..... @vvv
xvor_v 0111 01010010 01101 ..... ..... ..... @vvv
xvxor_v 0111 01010010 01110 ..... ..... ..... @vvv
xvnor_v 0111 01010010 01111 ..... ..... ..... @vvv
xvandn_v 0111 01010010 10000 ..... ..... ..... @vvv
xvorn_v 0111 01010010 10001 ..... ..... ..... @vvv
xvandi_b 0111 01111101 00 ........ ..... ..... @vv_ui8
xvori_b 0111 01111101 01 ........ ..... ..... @vv_ui8
xvxori_b 0111 01111101 10 ........ ..... ..... @vv_ui8
xvnori_b 0111 01111101 11 ........ ..... ..... @vv_ui8
target/loongarch: Implement xvsll xvsrl xvsra xvrotr This patch includes: - XVSLL[I].{B/H/W/D}; - XVSRL[I].{B/H/W/D}; - XVSRA[I].{B/H/W/D}; - XVROTR[I].{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-36-gaosong@loongson.cn>
2023-09-14 05:26:23 +03:00
xvsll_b 0111 01001110 10000 ..... ..... ..... @vvv
xvsll_h 0111 01001110 10001 ..... ..... ..... @vvv
xvsll_w 0111 01001110 10010 ..... ..... ..... @vvv
xvsll_d 0111 01001110 10011 ..... ..... ..... @vvv
xvslli_b 0111 01110010 11000 01 ... ..... ..... @vv_ui3
xvslli_h 0111 01110010 11000 1 .... ..... ..... @vv_ui4
xvslli_w 0111 01110010 11001 ..... ..... ..... @vv_ui5
xvslli_d 0111 01110010 1101 ...... ..... ..... @vv_ui6
xvsrl_b 0111 01001110 10100 ..... ..... ..... @vvv
xvsrl_h 0111 01001110 10101 ..... ..... ..... @vvv
xvsrl_w 0111 01001110 10110 ..... ..... ..... @vvv
xvsrl_d 0111 01001110 10111 ..... ..... ..... @vvv
xvsrli_b 0111 01110011 00000 01 ... ..... ..... @vv_ui3
xvsrli_h 0111 01110011 00000 1 .... ..... ..... @vv_ui4
xvsrli_w 0111 01110011 00001 ..... ..... ..... @vv_ui5
xvsrli_d 0111 01110011 0001 ...... ..... ..... @vv_ui6
xvsra_b 0111 01001110 11000 ..... ..... ..... @vvv
xvsra_h 0111 01001110 11001 ..... ..... ..... @vvv
xvsra_w 0111 01001110 11010 ..... ..... ..... @vvv
xvsra_d 0111 01001110 11011 ..... ..... ..... @vvv
xvsrai_b 0111 01110011 01000 01 ... ..... ..... @vv_ui3
xvsrai_h 0111 01110011 01000 1 .... ..... ..... @vv_ui4
xvsrai_w 0111 01110011 01001 ..... ..... ..... @vv_ui5
xvsrai_d 0111 01110011 0101 ...... ..... ..... @vv_ui6
xvrotr_b 0111 01001110 11100 ..... ..... ..... @vvv
xvrotr_h 0111 01001110 11101 ..... ..... ..... @vvv
xvrotr_w 0111 01001110 11110 ..... ..... ..... @vvv
xvrotr_d 0111 01001110 11111 ..... ..... ..... @vvv
xvrotri_b 0111 01101010 00000 01 ... ..... ..... @vv_ui3
xvrotri_h 0111 01101010 00000 1 .... ..... ..... @vv_ui4
xvrotri_w 0111 01101010 00001 ..... ..... ..... @vv_ui5
xvrotri_d 0111 01101010 0001 ...... ..... ..... @vv_ui6
target/loongarch: Implement xvsllwil xvextl This patch includes: - XVSLLWIL.{H.B/W.H/D.W}; - XVSLLWIL.{HU.BU/WU.HU/DU.WU}; - XVEXTL.Q.D, VEXTL.QU.DU. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-37-gaosong@loongson.cn>
2023-09-14 05:26:24 +03:00
xvsllwil_h_b 0111 01110000 10000 01 ... ..... ..... @vv_ui3
xvsllwil_w_h 0111 01110000 10000 1 .... ..... ..... @vv_ui4
xvsllwil_d_w 0111 01110000 10001 ..... ..... ..... @vv_ui5
xvextl_q_d 0111 01110000 10010 00000 ..... ..... @vv
xvsllwil_hu_bu 0111 01110000 11000 01 ... ..... ..... @vv_ui3
xvsllwil_wu_hu 0111 01110000 11000 1 .... ..... ..... @vv_ui4
xvsllwil_du_wu 0111 01110000 11001 ..... ..... ..... @vv_ui5
xvextl_qu_du 0111 01110000 11010 00000 ..... ..... @vv
target/loongarch: Implement xvsrlr xvsrar This patch includes: - XVSRLR[I].{B/H/W/D}; - XVSRAR[I].{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-38-gaosong@loongson.cn>
2023-09-14 05:26:25 +03:00
xvsrlr_b 0111 01001111 00000 ..... ..... ..... @vvv
xvsrlr_h 0111 01001111 00001 ..... ..... ..... @vvv
xvsrlr_w 0111 01001111 00010 ..... ..... ..... @vvv
xvsrlr_d 0111 01001111 00011 ..... ..... ..... @vvv
xvsrlri_b 0111 01101010 01000 01 ... ..... ..... @vv_ui3
xvsrlri_h 0111 01101010 01000 1 .... ..... ..... @vv_ui4
xvsrlri_w 0111 01101010 01001 ..... ..... ..... @vv_ui5
xvsrlri_d 0111 01101010 0101 ...... ..... ..... @vv_ui6
xvsrar_b 0111 01001111 00100 ..... ..... ..... @vvv
xvsrar_h 0111 01001111 00101 ..... ..... ..... @vvv
xvsrar_w 0111 01001111 00110 ..... ..... ..... @vvv
xvsrar_d 0111 01001111 00111 ..... ..... ..... @vvv
xvsrari_b 0111 01101010 10000 01 ... ..... ..... @vv_ui3
xvsrari_h 0111 01101010 10000 1 .... ..... ..... @vv_ui4
xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5
xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement xvsrln xvsran This patch includes: - XVSRLN.{B.H/H.W/W.D}; - XVSRAN.{B.H/H.W/W.D}; - XVSRLNI.{B.H/H.W/W.D/D.Q}; - XVSRANI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-39-gaosong@loongson.cn>
2023-09-14 05:26:26 +03:00
xvsrln_b_h 0111 01001111 01001 ..... ..... ..... @vvv
xvsrln_h_w 0111 01001111 01010 ..... ..... ..... @vvv
xvsrln_w_d 0111 01001111 01011 ..... ..... ..... @vvv
xvsran_b_h 0111 01001111 01101 ..... ..... ..... @vvv
xvsran_h_w 0111 01001111 01110 ..... ..... ..... @vvv
xvsran_w_d 0111 01001111 01111 ..... ..... ..... @vvv
xvsrlni_b_h 0111 01110100 00000 1 .... ..... ..... @vv_ui4
xvsrlni_h_w 0111 01110100 00001 ..... ..... ..... @vv_ui5
xvsrlni_w_d 0111 01110100 0001 ...... ..... ..... @vv_ui6
xvsrlni_d_q 0111 01110100 001 ....... ..... ..... @vv_ui7
xvsrani_b_h 0111 01110101 10000 1 .... ..... ..... @vv_ui4
xvsrani_h_w 0111 01110101 10001 ..... ..... ..... @vv_ui5
xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6
xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7
target/loongarch: Implement xvsrlrn xvsrarn This patch includes: - XVSRLRN.{B.H/H.W/W.D}; - XVSRARN.{B.H/H.W/W.D}; - XVSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSRARNI.{B.H/H.W/W.D/D.Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-40-gaosong@loongson.cn>
2023-09-14 05:26:27 +03:00
xvsrlrn_b_h 0111 01001111 10001 ..... ..... ..... @vvv
xvsrlrn_h_w 0111 01001111 10010 ..... ..... ..... @vvv
xvsrlrn_w_d 0111 01001111 10011 ..... ..... ..... @vvv
xvsrarn_b_h 0111 01001111 10101 ..... ..... ..... @vvv
xvsrarn_h_w 0111 01001111 10110 ..... ..... ..... @vvv
xvsrarn_w_d 0111 01001111 10111 ..... ..... ..... @vvv
xvsrlrni_b_h 0111 01110100 01000 1 .... ..... ..... @vv_ui4
xvsrlrni_h_w 0111 01110100 01001 ..... ..... ..... @vv_ui5
xvsrlrni_w_d 0111 01110100 0101 ...... ..... ..... @vv_ui6
xvsrlrni_d_q 0111 01110100 011 ....... ..... ..... @vv_ui7
xvsrarni_b_h 0111 01110101 11000 1 .... ..... ..... @vv_ui4
xvsrarni_h_w 0111 01110101 11001 ..... ..... ..... @vv_ui5
xvsrarni_w_d 0111 01110101 1101 ...... ..... ..... @vv_ui6
xvsrarni_d_q 0111 01110101 111 ....... ..... ..... @vv_ui7
target/loongarch: Implement xvssrln xvssran This patch includes: - XVSSRLN.{B.H/H.W/W.D}; - XVSSRAN.{B.H/H.W/W.D}; - XVSSRLN.{BU.H/HU.W/WU.D}; - XVSSRAN.{BU.H/HU.W/WU.D}; - XVSSRLNI.{B.H/H.W/W.D/D.Q}; - XVSSRANI.{B.H/H.W/W.D/D.Q}; - XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-41-gaosong@loongson.cn>
2023-09-14 05:26:28 +03:00
xvssrln_b_h 0111 01001111 11001 ..... ..... ..... @vvv
xvssrln_h_w 0111 01001111 11010 ..... ..... ..... @vvv
xvssrln_w_d 0111 01001111 11011 ..... ..... ..... @vvv
xvssran_b_h 0111 01001111 11101 ..... ..... ..... @vvv
xvssran_h_w 0111 01001111 11110 ..... ..... ..... @vvv
xvssran_w_d 0111 01001111 11111 ..... ..... ..... @vvv
xvssrln_bu_h 0111 01010000 01001 ..... ..... ..... @vvv
xvssrln_hu_w 0111 01010000 01010 ..... ..... ..... @vvv
xvssrln_wu_d 0111 01010000 01011 ..... ..... ..... @vvv
xvssran_bu_h 0111 01010000 01101 ..... ..... ..... @vvv
xvssran_hu_w 0111 01010000 01110 ..... ..... ..... @vvv
xvssran_wu_d 0111 01010000 01111 ..... ..... ..... @vvv
xvssrlni_b_h 0111 01110100 10000 1 .... ..... ..... @vv_ui4
xvssrlni_h_w 0111 01110100 10001 ..... ..... ..... @vv_ui5
xvssrlni_w_d 0111 01110100 1001 ...... ..... ..... @vv_ui6
xvssrlni_d_q 0111 01110100 101 ....... ..... ..... @vv_ui7
xvssrani_b_h 0111 01110110 00000 1 .... ..... ..... @vv_ui4
xvssrani_h_w 0111 01110110 00001 ..... ..... ..... @vv_ui5
xvssrani_w_d 0111 01110110 0001 ...... ..... ..... @vv_ui6
xvssrani_d_q 0111 01110110 001 ....... ..... ..... @vv_ui7
xvssrlni_bu_h 0111 01110100 11000 1 .... ..... ..... @vv_ui4
xvssrlni_hu_w 0111 01110100 11001 ..... ..... ..... @vv_ui5
xvssrlni_wu_d 0111 01110100 1101 ...... ..... ..... @vv_ui6
xvssrlni_du_q 0111 01110100 111 ....... ..... ..... @vv_ui7
xvssrani_bu_h 0111 01110110 01000 1 .... ..... ..... @vv_ui4
xvssrani_hu_w 0111 01110110 01001 ..... ..... ..... @vv_ui5
xvssrani_wu_d 0111 01110110 0101 ...... ..... ..... @vv_ui6
xvssrani_du_q 0111 01110110 011 ....... ..... ..... @vv_ui7
target/loongarch: Implement xvssrlrn xvssrarn This patch includes: - XVSSRLRN.{B.H/H.W/W.D}; - XVSSRARN.{B.H/H.W/W.D}; - XVSSRLRN.{BU.H/HU.W/WU.D}; - XVSSRARN.{BU.H/HU.W/WU.D}; - XVSSRLRNI.{B.H/H.W/W.D/D.Q}; - XVSSRARNI.{B.H/H.W/W.D/D.Q}; - XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q}; - XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-42-gaosong@loongson.cn>
2023-09-14 05:26:29 +03:00
xvssrlrn_b_h 0111 01010000 00001 ..... ..... ..... @vvv
xvssrlrn_h_w 0111 01010000 00010 ..... ..... ..... @vvv
xvssrlrn_w_d 0111 01010000 00011 ..... ..... ..... @vvv
xvssrarn_b_h 0111 01010000 00101 ..... ..... ..... @vvv
xvssrarn_h_w 0111 01010000 00110 ..... ..... ..... @vvv
xvssrarn_w_d 0111 01010000 00111 ..... ..... ..... @vvv
xvssrlrn_bu_h 0111 01010000 10001 ..... ..... ..... @vvv
xvssrlrn_hu_w 0111 01010000 10010 ..... ..... ..... @vvv
xvssrlrn_wu_d 0111 01010000 10011 ..... ..... ..... @vvv
xvssrarn_bu_h 0111 01010000 10101 ..... ..... ..... @vvv
xvssrarn_hu_w 0111 01010000 10110 ..... ..... ..... @vvv
xvssrarn_wu_d 0111 01010000 10111 ..... ..... ..... @vvv
xvssrlrni_b_h 0111 01110101 00000 1 .... ..... ..... @vv_ui4
xvssrlrni_h_w 0111 01110101 00001 ..... ..... ..... @vv_ui5
xvssrlrni_w_d 0111 01110101 0001 ...... ..... ..... @vv_ui6
xvssrlrni_d_q 0111 01110101 001 ....... ..... ..... @vv_ui7
xvssrarni_b_h 0111 01110110 10000 1 .... ..... ..... @vv_ui4
xvssrarni_h_w 0111 01110110 10001 ..... ..... ..... @vv_ui5
xvssrarni_w_d 0111 01110110 1001 ...... ..... ..... @vv_ui6
xvssrarni_d_q 0111 01110110 101 ....... ..... ..... @vv_ui7
xvssrlrni_bu_h 0111 01110101 01000 1 .... ..... ..... @vv_ui4
xvssrlrni_hu_w 0111 01110101 01001 ..... ..... ..... @vv_ui5
xvssrlrni_wu_d 0111 01110101 0101 ...... ..... ..... @vv_ui6
xvssrlrni_du_q 0111 01110101 011 ....... ..... ..... @vv_ui7
xvssrarni_bu_h 0111 01110110 11000 1 .... ..... ..... @vv_ui4
xvssrarni_hu_w 0111 01110110 11001 ..... ..... ..... @vv_ui5
xvssrarni_wu_d 0111 01110110 1101 ...... ..... ..... @vv_ui6
xvssrarni_du_q 0111 01110110 111 ....... ..... ..... @vv_ui7
target/loongarch: Implement xvclo xvclz This patch includes: - XVCLO.{B/H/W/D}; - XVCLZ.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-43-gaosong@loongson.cn>
2023-09-14 05:26:30 +03:00
xvclo_b 0111 01101001 11000 00000 ..... ..... @vv
xvclo_h 0111 01101001 11000 00001 ..... ..... @vv
xvclo_w 0111 01101001 11000 00010 ..... ..... @vv
xvclo_d 0111 01101001 11000 00011 ..... ..... @vv
xvclz_b 0111 01101001 11000 00100 ..... ..... @vv
xvclz_h 0111 01101001 11000 00101 ..... ..... @vv
xvclz_w 0111 01101001 11000 00110 ..... ..... @vv
xvclz_d 0111 01101001 11000 00111 ..... ..... @vv
target/loongarch: Implement xvpcnt This patch includes: - VPCNT.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-44-gaosong@loongson.cn>
2023-09-14 05:26:31 +03:00
xvpcnt_b 0111 01101001 11000 01000 ..... ..... @vv
xvpcnt_h 0111 01101001 11000 01001 ..... ..... @vv
xvpcnt_w 0111 01101001 11000 01010 ..... ..... @vv
xvpcnt_d 0111 01101001 11000 01011 ..... ..... @vv
target/loongarch: Implement xvbitclr xvbitset xvbitrev This patch includes: - XVBITCLR[I].{B/H/W/D}; - XVBITSET[I].{B/H/W/D}; - XVBITREV[I].{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-45-gaosong@loongson.cn>
2023-09-14 05:26:32 +03:00
xvbitclr_b 0111 01010000 11000 ..... ..... ..... @vvv
xvbitclr_h 0111 01010000 11001 ..... ..... ..... @vvv
xvbitclr_w 0111 01010000 11010 ..... ..... ..... @vvv
xvbitclr_d 0111 01010000 11011 ..... ..... ..... @vvv
xvbitclri_b 0111 01110001 00000 01 ... ..... ..... @vv_ui3
xvbitclri_h 0111 01110001 00000 1 .... ..... ..... @vv_ui4
xvbitclri_w 0111 01110001 00001 ..... ..... ..... @vv_ui5
xvbitclri_d 0111 01110001 0001 ...... ..... ..... @vv_ui6
xvbitset_b 0111 01010000 11100 ..... ..... ..... @vvv
xvbitset_h 0111 01010000 11101 ..... ..... ..... @vvv
xvbitset_w 0111 01010000 11110 ..... ..... ..... @vvv
xvbitset_d 0111 01010000 11111 ..... ..... ..... @vvv
xvbitseti_b 0111 01110001 01000 01 ... ..... ..... @vv_ui3
xvbitseti_h 0111 01110001 01000 1 .... ..... ..... @vv_ui4
xvbitseti_w 0111 01110001 01001 ..... ..... ..... @vv_ui5
xvbitseti_d 0111 01110001 0101 ...... ..... ..... @vv_ui6
xvbitrev_b 0111 01010001 00000 ..... ..... ..... @vvv
xvbitrev_h 0111 01010001 00001 ..... ..... ..... @vvv
xvbitrev_w 0111 01010001 00010 ..... ..... ..... @vvv
xvbitrev_d 0111 01010001 00011 ..... ..... ..... @vvv
xvbitrevi_b 0111 01110001 10000 01 ... ..... ..... @vv_ui3
xvbitrevi_h 0111 01110001 10000 1 .... ..... ..... @vv_ui4
xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
target/loongarch: Implement xvfrstp This patch includes: - XVFRSTP[I].{B/H}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-46-gaosong@loongson.cn>
2023-09-14 05:26:33 +03:00
xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv
xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
target/loongarch: Implement LASX fpu arith instructions This patch includes: - XVF{ADD/SUB/MUL/DIV}.{S/D}; - XVF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - XVF{MAX/MIN}.{S/D}; - XVF{MAXA/MINA}.{S/D}; - XVFLOGB.{S/D}; - XVFCLASS.{S/D}; - XVF{SQRT/RECIP/RSQRT}.{S/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-47-gaosong@loongson.cn>
2023-09-14 05:26:34 +03:00
xvfadd_s 0111 01010011 00001 ..... ..... ..... @vvv
xvfadd_d 0111 01010011 00010 ..... ..... ..... @vvv
xvfsub_s 0111 01010011 00101 ..... ..... ..... @vvv
xvfsub_d 0111 01010011 00110 ..... ..... ..... @vvv
xvfmul_s 0111 01010011 10001 ..... ..... ..... @vvv
xvfmul_d 0111 01010011 10010 ..... ..... ..... @vvv
xvfdiv_s 0111 01010011 10101 ..... ..... ..... @vvv
xvfdiv_d 0111 01010011 10110 ..... ..... ..... @vvv
xvfmadd_s 0000 10100001 ..... ..... ..... ..... @vvvv
xvfmadd_d 0000 10100010 ..... ..... ..... ..... @vvvv
xvfmsub_s 0000 10100101 ..... ..... ..... ..... @vvvv
xvfmsub_d 0000 10100110 ..... ..... ..... ..... @vvvv
xvfnmadd_s 0000 10101001 ..... ..... ..... ..... @vvvv
xvfnmadd_d 0000 10101010 ..... ..... ..... ..... @vvvv
xvfnmsub_s 0000 10101101 ..... ..... ..... ..... @vvvv
xvfnmsub_d 0000 10101110 ..... ..... ..... ..... @vvvv
xvfmax_s 0111 01010011 11001 ..... ..... ..... @vvv
xvfmax_d 0111 01010011 11010 ..... ..... ..... @vvv
xvfmin_s 0111 01010011 11101 ..... ..... ..... @vvv
xvfmin_d 0111 01010011 11110 ..... ..... ..... @vvv
xvfmaxa_s 0111 01010100 00001 ..... ..... ..... @vvv
xvfmaxa_d 0111 01010100 00010 ..... ..... ..... @vvv
xvfmina_s 0111 01010100 00101 ..... ..... ..... @vvv
xvfmina_d 0111 01010100 00110 ..... ..... ..... @vvv
xvflogb_s 0111 01101001 11001 10001 ..... ..... @vv
xvflogb_d 0111 01101001 11001 10010 ..... ..... @vv
xvfclass_s 0111 01101001 11001 10101 ..... ..... @vv
xvfclass_d 0111 01101001 11001 10110 ..... ..... @vv
xvfsqrt_s 0111 01101001 11001 11001 ..... ..... @vv
xvfsqrt_d 0111 01101001 11001 11010 ..... ..... @vv
xvfrecip_s 0111 01101001 11001 11101 ..... ..... @vv
xvfrecip_d 0111 01101001 11001 11110 ..... ..... @vv
xvfrsqrt_s 0111 01101001 11010 00001 ..... ..... @vv
xvfrsqrt_d 0111 01101001 11010 00010 ..... ..... @vv
target/loongarch: Implement LASX fpu fcvt instructions This patch includes: - XVFCVT{L/H}.{S.H/D.S}; - XVFCVT.{H.S/S.D}; - XVFRINT[{RNE/RZ/RP/RM}].{S/D}; - XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - XVFTINT[RZ].{WU.S/LU.D}; - XVFTINT[{RNE/RZ/RP/RM}].W.D; - XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - XVFFINT.{S.W/D.L}[U]; - X[CVFFINT.S.L, VFFINT{L/H}.D.W. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-48-gaosong@loongson.cn>
2023-09-14 05:26:35 +03:00
xvfcvtl_s_h 0111 01101001 11011 11010 ..... ..... @vv
xvfcvth_s_h 0111 01101001 11011 11011 ..... ..... @vv
xvfcvtl_d_s 0111 01101001 11011 11100 ..... ..... @vv
xvfcvth_d_s 0111 01101001 11011 11101 ..... ..... @vv
xvfcvt_h_s 0111 01010100 01100 ..... ..... ..... @vvv
xvfcvt_s_d 0111 01010100 01101 ..... ..... ..... @vvv
xvfrintrne_s 0111 01101001 11010 11101 ..... ..... @vv
xvfrintrne_d 0111 01101001 11010 11110 ..... ..... @vv
xvfrintrz_s 0111 01101001 11010 11001 ..... ..... @vv
xvfrintrz_d 0111 01101001 11010 11010 ..... ..... @vv
xvfrintrp_s 0111 01101001 11010 10101 ..... ..... @vv
xvfrintrp_d 0111 01101001 11010 10110 ..... ..... @vv
xvfrintrm_s 0111 01101001 11010 10001 ..... ..... @vv
xvfrintrm_d 0111 01101001 11010 10010 ..... ..... @vv
xvfrint_s 0111 01101001 11010 01101 ..... ..... @vv
xvfrint_d 0111 01101001 11010 01110 ..... ..... @vv
xvftintrne_w_s 0111 01101001 11100 10100 ..... ..... @vv
xvftintrne_l_d 0111 01101001 11100 10101 ..... ..... @vv
xvftintrz_w_s 0111 01101001 11100 10010 ..... ..... @vv
xvftintrz_l_d 0111 01101001 11100 10011 ..... ..... @vv
xvftintrp_w_s 0111 01101001 11100 10000 ..... ..... @vv
xvftintrp_l_d 0111 01101001 11100 10001 ..... ..... @vv
xvftintrm_w_s 0111 01101001 11100 01110 ..... ..... @vv
xvftintrm_l_d 0111 01101001 11100 01111 ..... ..... @vv
xvftint_w_s 0111 01101001 11100 01100 ..... ..... @vv
xvftint_l_d 0111 01101001 11100 01101 ..... ..... @vv
xvftintrz_wu_s 0111 01101001 11100 11100 ..... ..... @vv
xvftintrz_lu_d 0111 01101001 11100 11101 ..... ..... @vv
xvftint_wu_s 0111 01101001 11100 10110 ..... ..... @vv
xvftint_lu_d 0111 01101001 11100 10111 ..... ..... @vv
xvftintrne_w_d 0111 01010100 10111 ..... ..... ..... @vvv
xvftintrz_w_d 0111 01010100 10110 ..... ..... ..... @vvv
xvftintrp_w_d 0111 01010100 10101 ..... ..... ..... @vvv
xvftintrm_w_d 0111 01010100 10100 ..... ..... ..... @vvv
xvftint_w_d 0111 01010100 10011 ..... ..... ..... @vvv
xvftintrnel_l_s 0111 01101001 11101 01000 ..... ..... @vv
xvftintrneh_l_s 0111 01101001 11101 01001 ..... ..... @vv
xvftintrzl_l_s 0111 01101001 11101 00110 ..... ..... @vv
xvftintrzh_l_s 0111 01101001 11101 00111 ..... ..... @vv
xvftintrpl_l_s 0111 01101001 11101 00100 ..... ..... @vv
xvftintrph_l_s 0111 01101001 11101 00101 ..... ..... @vv
xvftintrml_l_s 0111 01101001 11101 00010 ..... ..... @vv
xvftintrmh_l_s 0111 01101001 11101 00011 ..... ..... @vv
xvftintl_l_s 0111 01101001 11101 00000 ..... ..... @vv
xvftinth_l_s 0111 01101001 11101 00001 ..... ..... @vv
xvffint_s_w 0111 01101001 11100 00000 ..... ..... @vv
xvffint_d_l 0111 01101001 11100 00010 ..... ..... @vv
xvffint_s_wu 0111 01101001 11100 00001 ..... ..... @vv
xvffint_d_lu 0111 01101001 11100 00011 ..... ..... @vv
xvffintl_d_w 0111 01101001 11100 00100 ..... ..... @vv
xvffinth_d_w 0111 01101001 11100 00101 ..... ..... @vv
xvffint_s_l 0111 01010100 10000 ..... ..... ..... @vvv
target/loongarch: Implement xvseq xvsle xvslt This patch includes: - XVSEQ[I].{B/H/W/D}; - XVSLE[I].{B/H/W/D}[U]; - XVSLT[I].{B/H/W/D/}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-49-gaosong@loongson.cn>
2023-09-14 05:26:36 +03:00
xvseq_b 0111 01000000 00000 ..... ..... ..... @vvv
xvseq_h 0111 01000000 00001 ..... ..... ..... @vvv
xvseq_w 0111 01000000 00010 ..... ..... ..... @vvv
xvseq_d 0111 01000000 00011 ..... ..... ..... @vvv
xvseqi_b 0111 01101000 00000 ..... ..... ..... @vv_i5
xvseqi_h 0111 01101000 00001 ..... ..... ..... @vv_i5
xvseqi_w 0111 01101000 00010 ..... ..... ..... @vv_i5
xvseqi_d 0111 01101000 00011 ..... ..... ..... @vv_i5
xvsle_b 0111 01000000 00100 ..... ..... ..... @vvv
xvsle_h 0111 01000000 00101 ..... ..... ..... @vvv
xvsle_w 0111 01000000 00110 ..... ..... ..... @vvv
xvsle_d 0111 01000000 00111 ..... ..... ..... @vvv
xvslei_b 0111 01101000 00100 ..... ..... ..... @vv_i5
xvslei_h 0111 01101000 00101 ..... ..... ..... @vv_i5
xvslei_w 0111 01101000 00110 ..... ..... ..... @vv_i5
xvslei_d 0111 01101000 00111 ..... ..... ..... @vv_i5
xvsle_bu 0111 01000000 01000 ..... ..... ..... @vvv
xvsle_hu 0111 01000000 01001 ..... ..... ..... @vvv
xvsle_wu 0111 01000000 01010 ..... ..... ..... @vvv
xvsle_du 0111 01000000 01011 ..... ..... ..... @vvv
xvslei_bu 0111 01101000 01000 ..... ..... ..... @vv_ui5
xvslei_hu 0111 01101000 01001 ..... ..... ..... @vv_ui5
xvslei_wu 0111 01101000 01010 ..... ..... ..... @vv_ui5
xvslei_du 0111 01101000 01011 ..... ..... ..... @vv_ui5
xvslt_b 0111 01000000 01100 ..... ..... ..... @vvv
xvslt_h 0111 01000000 01101 ..... ..... ..... @vvv
xvslt_w 0111 01000000 01110 ..... ..... ..... @vvv
xvslt_d 0111 01000000 01111 ..... ..... ..... @vvv
xvslti_b 0111 01101000 01100 ..... ..... ..... @vv_i5
xvslti_h 0111 01101000 01101 ..... ..... ..... @vv_i5
xvslti_w 0111 01101000 01110 ..... ..... ..... @vv_i5
xvslti_d 0111 01101000 01111 ..... ..... ..... @vv_i5
xvslt_bu 0111 01000000 10000 ..... ..... ..... @vvv
xvslt_hu 0111 01000000 10001 ..... ..... ..... @vvv
xvslt_wu 0111 01000000 10010 ..... ..... ..... @vvv
xvslt_du 0111 01000000 10011 ..... ..... ..... @vvv
xvslti_bu 0111 01101000 10000 ..... ..... ..... @vv_ui5
xvslti_hu 0111 01101000 10001 ..... ..... ..... @vv_ui5
xvslti_wu 0111 01101000 10010 ..... ..... ..... @vv_ui5
xvslti_du 0111 01101000 10011 ..... ..... ..... @vv_ui5
target/loongarch: Implement xvfcmp This patch includes: - XVFCMP.cond.{S/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-50-gaosong@loongson.cn>
2023-09-14 05:26:37 +03:00
xvfcmp_cond_s 0000 11001001 ..... ..... ..... ..... @vvv_fcond
xvfcmp_cond_d 0000 11001010 ..... ..... ..... ..... @vvv_fcond
target/loongarch: Implement xvbitsel xvset This patch includes: - XVBITSEL.V; - XVBITSELI.B; - XVSET{EQZ/NEZ}.V; - XVSETANYEQZ.{B/H/W/D}; - XVSETALLNEZ.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-51-gaosong@loongson.cn>
2023-09-14 05:26:38 +03:00
xvbitsel_v 0000 11010010 ..... ..... ..... ..... @vvvv
xvbitseli_b 0111 01111100 01 ........ ..... ..... @vv_ui8
xvseteqz_v 0111 01101001 11001 00110 ..... 00 ... @cv
xvsetnez_v 0111 01101001 11001 00111 ..... 00 ... @cv
xvsetanyeqz_b 0111 01101001 11001 01000 ..... 00 ... @cv
xvsetanyeqz_h 0111 01101001 11001 01001 ..... 00 ... @cv
xvsetanyeqz_w 0111 01101001 11001 01010 ..... 00 ... @cv
xvsetanyeqz_d 0111 01101001 11001 01011 ..... 00 ... @cv
xvsetallnez_b 0111 01101001 11001 01100 ..... 00 ... @cv
xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ... @cv
xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cv
xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cv
target/loongarch: Implement xvinsgr2vr xvpickve2gr This patch includes: - XVINSGR2VR.{W/D}; - XVPICKVE2GR.{W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-52-gaosong@loongson.cn>
2023-09-14 05:26:39 +03:00
xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @vr_ui3
xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @vr_ui2
xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rv_ui3
xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rv_ui2
xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rv_ui3
xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rv_ui2
target/loongarch: Implement xvreplgr2vr This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-16-gaosong@loongson.cn>
2023-09-14 05:26:03 +03:00
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
xvreplgr2vr_d 0111 01101001 11110 00011 ..... ..... @vr
target/loongarch: Implement xvreplve xvinsve0 xvpickve This patch includes: - XVREPLVE.{B/H/W/D}; - XVREPL128VEI.{B/H/W/D}; - XVREPLVE0.{B/H/W/D/Q}; - XVINSVE0.{W/D}; - XVPICKVE.{W/D}; - XVBSLL.V, XVBSRL.V. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-53-gaosong@loongson.cn>
2023-09-14 05:26:40 +03:00
xvreplve_b 0111 01010010 00100 ..... ..... ..... @vvr
xvreplve_h 0111 01010010 00101 ..... ..... ..... @vvr
xvreplve_w 0111 01010010 00110 ..... ..... ..... @vvr
xvreplve_d 0111 01010010 00111 ..... ..... ..... @vvr
xvrepl128vei_b 0111 01101111 01111 0 .... ..... ..... @vv_ui4
xvrepl128vei_h 0111 01101111 01111 10 ... ..... ..... @vv_ui3
xvrepl128vei_w 0111 01101111 01111 110 .. ..... ..... @vv_ui2
xvrepl128vei_d 0111 01101111 01111 1110 . ..... ..... @vv_ui1
xvreplve0_b 0111 01110000 01110 00000 ..... ..... @vv
xvreplve0_h 0111 01110000 01111 00000 ..... ..... @vv
xvreplve0_w 0111 01110000 01111 10000 ..... ..... @vv
xvreplve0_d 0111 01110000 01111 11000 ..... ..... @vv
xvreplve0_q 0111 01110000 01111 11100 ..... ..... @vv
xvinsve0_w 0111 01101111 11111 10 ... ..... ..... @vv_ui3
xvinsve0_d 0111 01101111 11111 110 .. ..... ..... @vv_ui2
xvpickve_w 0111 01110000 00111 10 ... ..... ..... @vv_ui3
xvpickve_d 0111 01110000 00111 110 .. ..... ..... @vv_ui2
xvbsll_v 0111 01101000 11100 ..... ..... ..... @vv_ui5
xvbsrl_v 0111 01101000 11101 ..... ..... ..... @vv_ui5
target/loongarch: Implement xvpack xvpick xvilv{l/h} This patch includes: - XVPACK{EV/OD}.{B/H/W/D}; - XVPICK{EV/OD}.{B/H/W/D}; - XVILV{L/H}.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-54-gaosong@loongson.cn>
2023-09-14 05:26:41 +03:00
xvpackev_b 0111 01010001 01100 ..... ..... ..... @vvv
xvpackev_h 0111 01010001 01101 ..... ..... ..... @vvv
xvpackev_w 0111 01010001 01110 ..... ..... ..... @vvv
xvpackev_d 0111 01010001 01111 ..... ..... ..... @vvv
xvpackod_b 0111 01010001 10000 ..... ..... ..... @vvv
xvpackod_h 0111 01010001 10001 ..... ..... ..... @vvv
xvpackod_w 0111 01010001 10010 ..... ..... ..... @vvv
xvpackod_d 0111 01010001 10011 ..... ..... ..... @vvv
xvpickev_b 0111 01010001 11100 ..... ..... ..... @vvv
xvpickev_h 0111 01010001 11101 ..... ..... ..... @vvv
xvpickev_w 0111 01010001 11110 ..... ..... ..... @vvv
xvpickev_d 0111 01010001 11111 ..... ..... ..... @vvv
xvpickod_b 0111 01010010 00000 ..... ..... ..... @vvv
xvpickod_h 0111 01010010 00001 ..... ..... ..... @vvv
xvpickod_w 0111 01010010 00010 ..... ..... ..... @vvv
xvpickod_d 0111 01010010 00011 ..... ..... ..... @vvv
xvilvl_b 0111 01010001 10100 ..... ..... ..... @vvv
xvilvl_h 0111 01010001 10101 ..... ..... ..... @vvv
xvilvl_w 0111 01010001 10110 ..... ..... ..... @vvv
xvilvl_d 0111 01010001 10111 ..... ..... ..... @vvv
xvilvh_b 0111 01010001 11000 ..... ..... ..... @vvv
xvilvh_h 0111 01010001 11001 ..... ..... ..... @vvv
xvilvh_w 0111 01010001 11010 ..... ..... ..... @vvv
xvilvh_d 0111 01010001 11011 ..... ..... ..... @vvv
target/loongarch: Implement xvshuf xvperm{i} xvshuf4i This patch includes: - XVSHUF.{B/H/W/D}; - XVPERM.W; - XVSHUF4i.{B/H/W/D}; - XVPERMI.{W/D/Q}; - XVEXTRINS.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-55-gaosong@loongson.cn>
2023-09-14 05:26:42 +03:00
xvshuf_b 0000 11010110 ..... ..... ..... ..... @vvvv
xvshuf_h 0111 01010111 10101 ..... ..... ..... @vvv
xvshuf_w 0111 01010111 10110 ..... ..... ..... @vvv
xvshuf_d 0111 01010111 10111 ..... ..... ..... @vvv
xvperm_w 0111 01010111 11010 ..... ..... ..... @vvv
xvshuf4i_b 0111 01111001 00 ........ ..... ..... @vv_ui8
xvshuf4i_h 0111 01111001 01 ........ ..... ..... @vv_ui8
xvshuf4i_w 0111 01111001 10 ........ ..... ..... @vv_ui8
xvshuf4i_d 0111 01111001 11 ........ ..... ..... @vv_ui8
xvpermi_w 0111 01111110 01 ........ ..... ..... @vv_ui8
xvpermi_d 0111 01111110 10 ........ ..... ..... @vv_ui8
xvpermi_q 0111 01111110 11 ........ ..... ..... @vv_ui8
xvextrins_d 0111 01111000 00 ........ ..... ..... @vv_ui8
xvextrins_w 0111 01111000 01 ........ ..... ..... @vv_ui8
xvextrins_h 0111 01111000 10 ........ ..... ..... @vv_ui8
xvextrins_b 0111 01111000 11 ........ ..... ..... @vv_ui8
target/loongarch: Implement xvld xvst This patch includes: - XVLD[X], XVST[X]; - XVLDREPL.{B/H/W/D}; - XVSTELM.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-56-gaosong@loongson.cn>
2023-09-14 05:26:43 +03:00
xvld 0010 110010 ............ ..... ..... @vr_i12
xvst 0010 110011 ............ ..... ..... @vr_i12
xvldx 0011 10000100 10000 ..... ..... ..... @vrr
xvstx 0011 10000100 11000 ..... ..... ..... @vrr
xvldrepl_d 0011 00100001 0 ......... ..... ..... @vr_i9
xvldrepl_w 0011 00100010 .......... ..... ..... @vr_i10
xvldrepl_h 0011 0010010 ........... ..... ..... @vr_i11
xvldrepl_b 0011 001010 ............ ..... ..... @vr_i12
xvstelm_d 0011 00110001 .. ........ ..... ..... @vr_i8i2x
xvstelm_w 0011 0011001 ... ........ ..... ..... @vr_i8i3x
xvstelm_h 0011 001101 .... ........ ..... ..... @vr_i8i4x
xvstelm_b 0011 00111 ..... ........ ..... ..... @vr_i8i5x
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