2011-10-16 02:56:46 +04:00
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/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2016-01-26 21:17:21 +03:00
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#include "qemu/osdep.h"
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2018-06-25 15:42:13 +03:00
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#include "qemu/units.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2016-01-19 23:51:44 +03:00
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#include "cpu.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/boards.h"
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#include "hw/loader.h"
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2011-10-16 02:56:46 +04:00
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#include "elf.h"
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2012-12-17 21:19:49 +04:00
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/char/serial.h"
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2012-10-24 10:43:34 +04:00
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#include "net/net.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/block/flash.h"
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2017-01-26 16:19:46 +03:00
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#include "chardev/char.h"
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2014-06-23 18:45:43 +04:00
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#include "sysemu/device_tree.h"
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2014-06-21 16:14:56 +04:00
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#include "qemu/error-report.h"
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2018-02-01 14:18:46 +03:00
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#include "qemu/option.h"
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2014-06-21 10:39:58 +04:00
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#include "bootparam.h"
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2017-12-23 00:53:36 +03:00
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#include "xtensa_memory.h"
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2019-01-26 15:17:31 +03:00
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#include "hw/xtensa/mx_pic.h"
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2011-10-30 21:21:15 +04:00
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2018-01-11 22:58:51 +03:00
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typedef struct XtfpgaFlashDesc {
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hwaddr base;
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size_t size;
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size_t boot_base;
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size_t sector_size;
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} XtfpgaFlashDesc;
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2017-12-22 07:31:00 +03:00
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typedef struct XtfpgaBoardDesc {
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2018-01-11 22:58:51 +03:00
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const XtfpgaFlashDesc *flash;
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2011-10-30 21:21:15 +04:00
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size_t sram_size;
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2015-09-24 16:18:51 +03:00
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const hwaddr *io;
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2017-12-22 07:31:00 +03:00
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} XtfpgaBoardDesc;
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2011-10-16 02:56:46 +04:00
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2017-12-22 07:31:00 +03:00
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typedef struct XtfpgaFpgaState {
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2011-10-16 02:56:46 +04:00
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MemoryRegion iomem;
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2019-01-23 00:40:40 +03:00
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uint32_t freq;
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2011-10-16 02:56:46 +04:00
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uint32_t leds;
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uint32_t switches;
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2017-12-22 07:31:00 +03:00
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} XtfpgaFpgaState;
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2011-10-16 02:56:46 +04:00
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2017-12-22 07:31:00 +03:00
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static void xtfpga_fpga_reset(void *opaque)
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2011-10-16 02:56:46 +04:00
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{
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2017-12-22 07:31:00 +03:00
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XtfpgaFpgaState *s = opaque;
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2011-10-16 02:56:46 +04:00
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s->leds = 0;
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s->switches = 0;
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}
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2017-12-22 07:31:00 +03:00
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static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
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2011-10-16 02:56:46 +04:00
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unsigned size)
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{
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2017-12-22 07:31:00 +03:00
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XtfpgaFpgaState *s = opaque;
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2011-10-16 02:56:46 +04:00
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switch (addr) {
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case 0x0: /*build date code*/
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2011-10-30 21:18:27 +04:00
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return 0x09272011;
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2011-10-16 02:56:46 +04:00
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case 0x4: /*processor clock frequency, Hz*/
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2019-01-23 00:40:40 +03:00
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return s->freq;
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2011-10-16 02:56:46 +04:00
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case 0x8: /*LEDs (off = 0, on = 1)*/
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return s->leds;
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case 0xc: /*DIP switches (off = 0, on = 1)*/
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return s->switches;
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}
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return 0;
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}
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2017-12-22 07:31:00 +03:00
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static void xtfpga_fpga_write(void *opaque, hwaddr addr,
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2011-10-16 02:56:46 +04:00
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uint64_t val, unsigned size)
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{
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2017-12-22 07:31:00 +03:00
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XtfpgaFpgaState *s = opaque;
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2011-10-16 02:56:46 +04:00
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switch (addr) {
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case 0x8: /*LEDs (off = 0, on = 1)*/
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s->leds = val;
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break;
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case 0x10: /*board reset*/
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if (val == 0xdead) {
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2017-05-16 00:41:13 +03:00
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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2011-10-16 02:56:46 +04:00
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}
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break;
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}
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}
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2017-12-22 07:31:00 +03:00
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static const MemoryRegionOps xtfpga_fpga_ops = {
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.read = xtfpga_fpga_read,
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.write = xtfpga_fpga_write,
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2011-10-16 02:56:46 +04:00
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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2017-12-22 07:31:00 +03:00
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static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
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2019-01-23 00:40:40 +03:00
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hwaddr base, uint32_t freq)
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2011-10-16 02:56:46 +04:00
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{
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2017-12-22 07:31:00 +03:00
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XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
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2011-10-16 02:56:46 +04:00
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2017-12-22 07:31:00 +03:00
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memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
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2019-01-23 00:40:40 +03:00
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"xtfpga.fpga", 0x10000);
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2011-10-16 02:56:46 +04:00
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memory_region_add_subregion(address_space, base, &s->iomem);
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2019-01-23 00:40:40 +03:00
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s->freq = freq;
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2017-12-22 07:31:00 +03:00
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xtfpga_fpga_reset(s);
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qemu_register_reset(xtfpga_fpga_reset, s);
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2011-10-16 02:56:46 +04:00
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return s;
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}
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2017-12-22 07:31:00 +03:00
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static void xtfpga_net_init(MemoryRegion *address_space,
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2012-10-23 14:30:10 +04:00
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hwaddr base,
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hwaddr descriptors,
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hwaddr buffers,
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2011-10-16 02:56:46 +04:00
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qemu_irq irq, NICInfo *nd)
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{
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DeviceState *dev;
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SysBusDevice *s;
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MemoryRegion *ram;
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dev = qdev_create(NULL, "open_eth");
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qdev_set_nic_properties(dev, nd);
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qdev_init_nofail(dev);
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2013-01-20 05:47:33 +04:00
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s = SYS_BUS_DEVICE(dev);
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2011-10-16 02:56:46 +04:00
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sysbus_connect_irq(s, 0, irq);
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memory_region_add_subregion(address_space, base,
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sysbus_mmio_get_region(s, 0));
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memory_region_add_subregion(address_space, descriptors,
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sysbus_mmio_get_region(s, 1));
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ram = g_malloc(sizeof(*ram));
|
2018-06-25 15:42:13 +03:00
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memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
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Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
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err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
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&error_fatal);
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2011-12-20 17:59:12 +04:00
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vmstate_register_ram_global(ram);
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2011-10-16 02:56:46 +04:00
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memory_region_add_subregion(address_space, buffers, ram);
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}
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2015-09-27 18:21:19 +03:00
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static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
|
2017-12-22 07:31:00 +03:00
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const XtfpgaBoardDesc *board,
|
2015-09-27 18:21:19 +03:00
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DriveInfo *dinfo, int be)
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{
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SysBusDevice *s;
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DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
|
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qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
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&error_abort);
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qdev_prop_set_uint32(dev, "num-blocks",
|
2018-01-11 22:58:51 +03:00
|
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|
board->flash->size / board->flash->sector_size);
|
|
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|
qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
|
2016-07-06 09:31:32 +03:00
|
|
|
qdev_prop_set_uint8(dev, "width", 2);
|
2015-09-27 18:21:19 +03:00
|
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|
qdev_prop_set_bit(dev, "big-endian", be);
|
2017-12-22 07:31:00 +03:00
|
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|
qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
|
2015-09-27 18:21:19 +03:00
|
|
|
qdev_init_nofail(dev);
|
|
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|
s = SYS_BUS_DEVICE(dev);
|
2018-01-11 22:58:51 +03:00
|
|
|
memory_region_add_subregion(address_space, board->flash->base,
|
2015-09-27 18:21:19 +03:00
|
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
|
|
|
|
}
|
|
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|
|
2013-06-29 20:55:54 +04:00
|
|
|
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
|
2011-10-16 02:56:46 +04:00
|
|
|
{
|
2013-06-29 20:55:54 +04:00
|
|
|
XtensaCPU *cpu = opaque;
|
|
|
|
|
|
|
|
return cpu_get_phys_page_debug(CPU(cpu), addr);
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
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|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_reset(void *opaque)
|
2011-10-16 02:56:46 +04:00
|
|
|
{
|
2012-05-04 21:33:05 +04:00
|
|
|
XtensaCPU *cpu = opaque;
|
2012-02-08 06:03:33 +04:00
|
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|
|
2012-05-04 21:33:05 +04:00
|
|
|
cpu_reset(CPU(cpu));
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
|
2014-02-17 20:57:45 +04:00
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_io_write(void *opaque, hwaddr addr,
|
2014-02-17 20:57:45 +04:00
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static const MemoryRegionOps xtfpga_io_ops = {
|
|
|
|
.read = xtfpga_io_read,
|
|
|
|
.write = xtfpga_io_write,
|
2014-02-17 20:57:45 +04:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
|
2011-10-16 02:56:46 +04:00
|
|
|
{
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
int be = 1;
|
|
|
|
#else
|
|
|
|
int be = 0;
|
|
|
|
#endif
|
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
2012-05-04 21:31:25 +04:00
|
|
|
XtensaCPU *cpu = NULL;
|
2012-03-14 04:38:24 +04:00
|
|
|
CPUXtensaState *env = NULL;
|
2017-12-23 00:53:36 +03:00
|
|
|
MemoryRegion *system_io;
|
2019-01-26 15:17:31 +03:00
|
|
|
XtensaMxPic *mx_pic = NULL;
|
2019-01-26 15:12:30 +03:00
|
|
|
qemu_irq *extints;
|
2011-10-30 21:21:15 +04:00
|
|
|
DriveInfo *dinfo;
|
|
|
|
pflash_t *flash = NULL;
|
2014-06-23 18:42:39 +04:00
|
|
|
QemuOpts *machine_opts = qemu_get_machine_opts();
|
|
|
|
const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
|
|
|
|
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
|
2014-06-23 18:45:43 +04:00
|
|
|
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
|
2014-06-21 13:35:35 +04:00
|
|
|
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
|
2018-06-25 15:42:13 +03:00
|
|
|
const unsigned system_io_size = 224 * MiB;
|
2019-01-23 00:40:40 +03:00
|
|
|
uint32_t freq = 10000000;
|
2011-10-16 02:56:46 +04:00
|
|
|
int n;
|
|
|
|
|
2019-01-26 15:17:31 +03:00
|
|
|
if (smp_cpus > 1) {
|
|
|
|
mx_pic = xtensa_mx_pic_init(31);
|
|
|
|
qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
|
|
|
|
}
|
2011-10-16 02:56:46 +04:00
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
2019-01-21 03:26:07 +03:00
|
|
|
CPUXtensaState *cenv = NULL;
|
|
|
|
|
2017-10-05 16:51:00 +03:00
|
|
|
cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
|
2019-01-21 03:26:07 +03:00
|
|
|
cenv = &cpu->env;
|
|
|
|
if (!env) {
|
|
|
|
env = cenv;
|
2019-01-23 00:40:40 +03:00
|
|
|
freq = env->config->clock_freq_khz * 1000;
|
2019-01-21 03:26:07 +03:00
|
|
|
}
|
2012-05-04 21:31:25 +04:00
|
|
|
|
2019-01-26 15:17:31 +03:00
|
|
|
if (mx_pic) {
|
|
|
|
MemoryRegion *mx_eri;
|
|
|
|
|
|
|
|
mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
|
|
|
|
xtensa_get_extints(cenv),
|
|
|
|
xtensa_get_runstall(cenv));
|
|
|
|
memory_region_add_subregion(xtensa_get_er_region(cenv),
|
|
|
|
0, mx_eri);
|
|
|
|
}
|
2019-01-21 03:26:07 +03:00
|
|
|
cenv->sregs[PRID] = n;
|
2019-01-26 15:17:31 +03:00
|
|
|
xtensa_select_static_vectors(cenv, n != 0);
|
2017-12-22 07:31:00 +03:00
|
|
|
qemu_register_reset(xtfpga_reset, cpu);
|
2011-10-16 02:56:46 +04:00
|
|
|
/* Need MMU initialized prior to ELF loading,
|
|
|
|
* so that ELF gets loaded into virtual addresses
|
|
|
|
*/
|
2012-05-04 21:31:25 +04:00
|
|
|
cpu_reset(CPU(cpu));
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
2019-01-26 15:17:31 +03:00
|
|
|
if (smp_cpus > 1) {
|
|
|
|
extints = xtensa_mx_pic_get_extints(mx_pic);
|
|
|
|
} else {
|
|
|
|
extints = xtensa_get_extints(env);
|
|
|
|
}
|
2011-10-16 02:56:46 +04:00
|
|
|
|
2017-12-23 00:53:36 +03:00
|
|
|
if (env) {
|
|
|
|
XtensaMemory sysram = env->config->sysram;
|
|
|
|
|
|
|
|
sysram.location[0].size = machine->ram_size;
|
|
|
|
xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
|
|
|
|
system_memory);
|
|
|
|
xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
|
|
|
|
system_memory);
|
|
|
|
xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
|
|
|
|
system_memory);
|
|
|
|
xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
|
|
|
|
system_memory);
|
|
|
|
xtensa_create_memory_regions(&sysram, "xtensa.sysram",
|
|
|
|
system_memory);
|
|
|
|
}
|
2011-10-16 02:56:46 +04:00
|
|
|
|
|
|
|
system_io = g_malloc(sizeof(*system_io));
|
2017-12-22 07:31:00 +03:00
|
|
|
memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
|
2015-09-24 16:18:51 +03:00
|
|
|
system_io_size);
|
|
|
|
memory_region_add_subregion(system_memory, board->io[0], system_io);
|
|
|
|
if (board->io[1]) {
|
|
|
|
MemoryRegion *io = g_malloc(sizeof(*io));
|
|
|
|
|
|
|
|
memory_region_init_alias(io, NULL, "xtfpga.io.cached",
|
|
|
|
system_io, 0, system_io_size);
|
|
|
|
memory_region_add_subregion(system_memory, board->io[1], io);
|
|
|
|
}
|
2019-01-23 00:40:40 +03:00
|
|
|
xtfpga_fpga_init(system_io, 0x0d020000, freq);
|
2012-07-24 19:35:11 +04:00
|
|
|
if (nd_table[0].used) {
|
2017-12-22 07:31:00 +03:00
|
|
|
xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
|
2019-01-26 15:12:30 +03:00
|
|
|
extints[1], nd_table);
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
|
|
|
2019-01-26 15:12:30 +03:00
|
|
|
serial_mm_init(system_io, 0x0d050020, 2, extints[0],
|
|
|
|
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
2011-10-16 02:56:46 +04:00
|
|
|
|
2011-10-30 21:21:15 +04:00
|
|
|
dinfo = drive_get(IF_PFLASH, 0, 0);
|
|
|
|
if (dinfo) {
|
2015-09-27 18:21:19 +03:00
|
|
|
flash = xtfpga_flash_init(system_io, board, dinfo, be);
|
2011-10-30 21:21:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Use presence of kernel file name as 'boot from SRAM' switch. */
|
2011-10-16 02:56:46 +04:00
|
|
|
if (kernel_filename) {
|
2013-03-04 07:07:52 +04:00
|
|
|
uint32_t entry_point = env->pc;
|
2014-06-23 17:24:48 +04:00
|
|
|
size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
|
2017-12-23 00:53:36 +03:00
|
|
|
uint32_t tagptr = env->config->sysrom.location[0].addr +
|
|
|
|
board->sram_size;
|
2014-06-21 13:10:38 +04:00
|
|
|
uint32_t cur_tagptr;
|
2014-06-23 17:24:48 +04:00
|
|
|
BpMemInfo memory_location = {
|
|
|
|
.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
|
2017-12-23 00:53:36 +03:00
|
|
|
.start = tswap32(env->config->sysram.location[0].addr),
|
|
|
|
.end = tswap32(env->config->sysram.location[0].addr +
|
|
|
|
machine->ram_size),
|
2014-06-23 17:24:48 +04:00
|
|
|
};
|
2014-06-23 18:45:43 +04:00
|
|
|
uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
|
|
|
|
machine->ram_size : 0x08000000;
|
|
|
|
uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
|
2014-06-21 13:10:38 +04:00
|
|
|
|
2017-12-23 00:53:36 +03:00
|
|
|
lowmem_end += env->config->sysram.location[0].addr;
|
|
|
|
cur_lowmem += env->config->sysram.location[0].addr;
|
|
|
|
|
|
|
|
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
|
|
|
|
system_memory);
|
2011-10-30 21:24:26 +04:00
|
|
|
|
2014-06-21 13:10:38 +04:00
|
|
|
if (kernel_cmdline) {
|
|
|
|
bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
|
|
|
|
}
|
2014-06-23 18:45:43 +04:00
|
|
|
if (dtb_filename) {
|
|
|
|
bp_size += get_tag_size(sizeof(uint32_t));
|
|
|
|
}
|
2014-06-21 13:35:35 +04:00
|
|
|
if (initrd_filename) {
|
|
|
|
bp_size += get_tag_size(sizeof(BpMemInfo));
|
|
|
|
}
|
2014-06-21 13:10:38 +04:00
|
|
|
|
2011-10-30 21:24:26 +04:00
|
|
|
/* Put kernel bootparameters to the end of that SRAM */
|
2014-06-21 13:10:38 +04:00
|
|
|
tagptr = (tagptr - bp_size) & ~0xff;
|
|
|
|
cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
|
2014-06-23 17:24:48 +04:00
|
|
|
cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
|
|
|
|
sizeof(memory_location), &memory_location);
|
2014-06-21 13:10:38 +04:00
|
|
|
|
2011-10-30 21:24:26 +04:00
|
|
|
if (kernel_cmdline) {
|
2014-06-21 13:10:38 +04:00
|
|
|
cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
|
|
|
|
strlen(kernel_cmdline) + 1, kernel_cmdline);
|
2011-10-30 21:24:26 +04:00
|
|
|
}
|
2017-03-11 22:24:44 +03:00
|
|
|
#ifdef CONFIG_FDT
|
2014-06-23 18:45:43 +04:00
|
|
|
if (dtb_filename) {
|
|
|
|
int fdt_size;
|
|
|
|
void *fdt = load_device_tree(dtb_filename, &fdt_size);
|
|
|
|
uint32_t dtb_addr = tswap32(cur_lowmem);
|
|
|
|
|
|
|
|
if (!fdt) {
|
2015-02-25 07:22:34 +03:00
|
|
|
error_report("could not load DTB '%s'", dtb_filename);
|
2014-06-23 18:45:43 +04:00
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
|
|
|
|
cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
|
|
|
|
sizeof(dtb_addr), &dtb_addr);
|
2018-06-25 15:42:13 +03:00
|
|
|
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
|
2014-06-23 18:45:43 +04:00
|
|
|
}
|
2017-03-11 22:24:44 +03:00
|
|
|
#else
|
|
|
|
if (dtb_filename) {
|
|
|
|
error_report("could not load DTB '%s': "
|
|
|
|
"FDT support is not configured in QEMU",
|
|
|
|
dtb_filename);
|
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
#endif
|
2014-06-21 13:35:35 +04:00
|
|
|
if (initrd_filename) {
|
|
|
|
BpMemInfo initrd_location = { 0 };
|
|
|
|
int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
|
|
|
|
lowmem_end - cur_lowmem);
|
|
|
|
|
|
|
|
if (initrd_size < 0) {
|
|
|
|
initrd_size = load_image_targphys(initrd_filename,
|
|
|
|
cur_lowmem,
|
|
|
|
lowmem_end - cur_lowmem);
|
|
|
|
}
|
|
|
|
if (initrd_size < 0) {
|
2015-02-25 07:22:34 +03:00
|
|
|
error_report("could not load initrd '%s'", initrd_filename);
|
2014-06-21 13:35:35 +04:00
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
initrd_location.start = tswap32(cur_lowmem);
|
|
|
|
initrd_location.end = tswap32(cur_lowmem + initrd_size);
|
|
|
|
cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
|
|
|
|
sizeof(initrd_location), &initrd_location);
|
2018-06-25 15:42:13 +03:00
|
|
|
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
|
2014-06-21 13:35:35 +04:00
|
|
|
}
|
2014-06-21 13:10:38 +04:00
|
|
|
cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
|
|
|
|
env->regs[2] = tagptr;
|
|
|
|
|
2011-10-16 02:56:46 +04:00
|
|
|
uint64_t elf_entry;
|
|
|
|
uint64_t elf_lowaddr;
|
2019-01-15 15:18:03 +03:00
|
|
|
int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
|
2016-03-04 14:30:21 +03:00
|
|
|
&elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
|
2011-10-16 02:56:46 +04:00
|
|
|
if (success > 0) {
|
2013-03-04 07:07:52 +04:00
|
|
|
entry_point = elf_entry;
|
|
|
|
} else {
|
|
|
|
hwaddr ep;
|
|
|
|
int is_linux;
|
2014-10-19 07:42:22 +04:00
|
|
|
success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
|
2014-10-19 08:39:10 +04:00
|
|
|
translate_phys_addr, cpu);
|
2013-03-04 07:07:52 +04:00
|
|
|
if (success > 0 && is_linux) {
|
|
|
|
entry_point = ep;
|
|
|
|
} else {
|
2015-02-25 07:22:34 +03:00
|
|
|
error_report("could not load kernel '%s'",
|
2013-03-04 07:07:52 +04:00
|
|
|
kernel_filename);
|
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (entry_point != env->pc) {
|
2017-12-22 07:51:05 +03:00
|
|
|
uint8_t boot[] = {
|
2013-03-04 07:07:52 +04:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2017-12-22 07:51:05 +03:00
|
|
|
0x60, 0x00, 0x08, /* j 1f */
|
|
|
|
0x00, /* .literal_position */
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
|
|
|
|
/* 1: */
|
|
|
|
0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
|
|
|
|
0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
|
|
|
|
0x0a, 0x00, 0x00, /* jx a0 */
|
2013-03-04 07:07:52 +04:00
|
|
|
#else
|
2017-12-22 07:51:05 +03:00
|
|
|
0x06, 0x02, 0x00, /* j 1f */
|
|
|
|
0x00, /* .literal_position */
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
|
|
|
|
/* 1: */
|
|
|
|
0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
|
|
|
|
0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
|
|
|
|
0xa0, 0x00, 0x00, /* jx a0 */
|
2013-03-04 07:07:52 +04:00
|
|
|
#endif
|
|
|
|
};
|
2017-12-22 07:51:05 +03:00
|
|
|
uint32_t entry_pc = tswap32(entry_point);
|
|
|
|
uint32_t entry_a2 = tswap32(tagptr);
|
|
|
|
|
|
|
|
memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
|
|
|
|
memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
|
|
|
|
cpu_physical_memory_write(env->pc, boot, sizeof(boot));
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
2011-10-30 21:21:15 +04:00
|
|
|
} else {
|
|
|
|
if (flash) {
|
|
|
|
MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
|
|
|
|
MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
|
2017-12-23 00:53:36 +03:00
|
|
|
uint32_t size = env->config->sysrom.location[0].size;
|
|
|
|
|
2018-01-11 22:58:51 +03:00
|
|
|
if (board->flash->size - board->flash->boot_base < size) {
|
|
|
|
size = board->flash->size - board->flash->boot_base;
|
2017-12-23 00:53:36 +03:00
|
|
|
}
|
2011-10-30 21:21:15 +04:00
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
|
2018-01-11 22:58:51 +03:00
|
|
|
flash_mr, board->flash->boot_base, size);
|
2017-12-23 00:53:36 +03:00
|
|
|
memory_region_add_subregion(system_memory,
|
|
|
|
env->config->sysrom.location[0].addr,
|
|
|
|
flash_io);
|
|
|
|
} else {
|
|
|
|
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
|
|
|
|
system_memory);
|
2011-10-30 21:21:15 +04:00
|
|
|
}
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-11-20 23:31:24 +03:00
|
|
|
#define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
|
|
|
|
|
2015-09-24 16:18:51 +03:00
|
|
|
static const hwaddr xtfpga_mmu_io[2] = {
|
|
|
|
0xf0000000,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const hwaddr xtfpga_nommu_io[2] = {
|
|
|
|
0x90000000,
|
|
|
|
0x70000000,
|
|
|
|
};
|
|
|
|
|
2018-01-11 22:58:51 +03:00
|
|
|
static const XtfpgaFlashDesc lx60_flash = {
|
|
|
|
.base = 0x08000000,
|
|
|
|
.size = 0x00400000,
|
|
|
|
.sector_size = 0x10000,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_lx60_init(MachineState *machine)
|
2011-10-16 02:56:46 +04:00
|
|
|
{
|
2017-12-22 07:31:00 +03:00
|
|
|
static const XtfpgaBoardDesc lx60_board = {
|
2018-01-11 22:58:51 +03:00
|
|
|
.flash = &lx60_flash,
|
2011-10-30 21:21:15 +04:00
|
|
|
.sram_size = 0x20000,
|
2015-09-24 16:18:51 +03:00
|
|
|
.io = xtfpga_mmu_io,
|
|
|
|
};
|
|
|
|
xtfpga_init(&lx60_board, machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xtfpga_lx60_nommu_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
static const XtfpgaBoardDesc lx60_board = {
|
|
|
|
.flash = &lx60_flash,
|
|
|
|
.sram_size = 0x20000,
|
|
|
|
.io = xtfpga_nommu_io,
|
2011-10-30 21:21:15 +04:00
|
|
|
};
|
2017-12-22 07:31:00 +03:00
|
|
|
xtfpga_init(&lx60_board, machine);
|
2011-10-30 21:21:15 +04:00
|
|
|
}
|
|
|
|
|
2018-01-11 22:58:51 +03:00
|
|
|
static const XtfpgaFlashDesc lx200_flash = {
|
|
|
|
.base = 0x08000000,
|
|
|
|
.size = 0x01000000,
|
|
|
|
.sector_size = 0x20000,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_lx200_init(MachineState *machine)
|
2011-10-30 21:21:15 +04:00
|
|
|
{
|
2017-12-22 07:31:00 +03:00
|
|
|
static const XtfpgaBoardDesc lx200_board = {
|
2018-01-11 22:58:51 +03:00
|
|
|
.flash = &lx200_flash,
|
2011-10-30 21:21:15 +04:00
|
|
|
.sram_size = 0x2000000,
|
2015-09-24 16:18:51 +03:00
|
|
|
.io = xtfpga_mmu_io,
|
|
|
|
};
|
|
|
|
xtfpga_init(&lx200_board, machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xtfpga_lx200_nommu_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
static const XtfpgaBoardDesc lx200_board = {
|
|
|
|
.flash = &lx200_flash,
|
|
|
|
.sram_size = 0x2000000,
|
|
|
|
.io = xtfpga_nommu_io,
|
2011-10-30 21:21:15 +04:00
|
|
|
};
|
2017-12-22 07:31:00 +03:00
|
|
|
xtfpga_init(&lx200_board, machine);
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
|
|
|
2018-01-11 22:58:51 +03:00
|
|
|
static const XtfpgaFlashDesc ml605_flash = {
|
|
|
|
.base = 0x08000000,
|
|
|
|
.size = 0x01000000,
|
|
|
|
.sector_size = 0x20000,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_ml605_init(MachineState *machine)
|
2014-02-02 02:44:41 +04:00
|
|
|
{
|
2017-12-22 07:31:00 +03:00
|
|
|
static const XtfpgaBoardDesc ml605_board = {
|
2018-01-11 22:58:51 +03:00
|
|
|
.flash = &ml605_flash,
|
2014-02-02 02:44:41 +04:00
|
|
|
.sram_size = 0x2000000,
|
2015-09-24 16:18:51 +03:00
|
|
|
.io = xtfpga_mmu_io,
|
|
|
|
};
|
|
|
|
xtfpga_init(&ml605_board, machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xtfpga_ml605_nommu_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
static const XtfpgaBoardDesc ml605_board = {
|
|
|
|
.flash = &ml605_flash,
|
|
|
|
.sram_size = 0x2000000,
|
|
|
|
.io = xtfpga_nommu_io,
|
2014-02-02 02:44:41 +04:00
|
|
|
};
|
2017-12-22 07:31:00 +03:00
|
|
|
xtfpga_init(&ml605_board, machine);
|
2014-02-02 02:44:41 +04:00
|
|
|
}
|
|
|
|
|
2018-01-11 22:58:51 +03:00
|
|
|
static const XtfpgaFlashDesc kc705_flash = {
|
|
|
|
.base = 0x00000000,
|
|
|
|
.size = 0x08000000,
|
|
|
|
.boot_base = 0x06000000,
|
|
|
|
.sector_size = 0x20000,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_kc705_init(MachineState *machine)
|
2014-02-02 02:44:41 +04:00
|
|
|
{
|
2017-12-22 07:31:00 +03:00
|
|
|
static const XtfpgaBoardDesc kc705_board = {
|
2018-01-11 22:58:51 +03:00
|
|
|
.flash = &kc705_flash,
|
2014-02-02 02:44:41 +04:00
|
|
|
.sram_size = 0x2000000,
|
2015-09-24 16:18:51 +03:00
|
|
|
.io = xtfpga_mmu_io,
|
|
|
|
};
|
|
|
|
xtfpga_init(&kc705_board, machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xtfpga_kc705_nommu_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
static const XtfpgaBoardDesc kc705_board = {
|
|
|
|
.flash = &kc705_flash,
|
|
|
|
.sram_size = 0x2000000,
|
|
|
|
.io = xtfpga_nommu_io,
|
2014-02-02 02:44:41 +04:00
|
|
|
};
|
2017-12-22 07:31:00 +03:00
|
|
|
xtfpga_init(&kc705_board, machine);
|
2014-02-02 02:44:41 +04:00
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
|
2015-09-04 21:37:08 +03:00
|
|
|
{
|
2015-09-19 11:49:44 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
2017-12-22 07:31:00 +03:00
|
|
|
mc->init = xtfpga_lx60_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2017-10-05 16:51:00 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 64 * MiB;
|
2015-09-04 21:37:08 +03:00
|
|
|
}
|
2011-10-16 02:56:46 +04:00
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static const TypeInfo xtfpga_lx60_type = {
|
2015-09-19 11:49:44 +03:00
|
|
|
.name = MACHINE_TYPE_NAME("lx60"),
|
|
|
|
.parent = TYPE_MACHINE,
|
2017-12-22 07:31:00 +03:00
|
|
|
.class_init = xtfpga_lx60_class_init,
|
2015-09-19 11:49:44 +03:00
|
|
|
};
|
2011-10-30 21:21:15 +04:00
|
|
|
|
2015-09-24 16:18:51 +03:00
|
|
|
static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
2015-09-24 16:18:51 +03:00
|
|
|
mc->init = xtfpga_lx60_nommu_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 64 * MiB;
|
2015-09-24 16:18:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xtfpga_lx60_nommu_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("lx60-nommu"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = xtfpga_lx60_nommu_class_init,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
|
2015-09-04 21:37:08 +03:00
|
|
|
{
|
2015-09-19 11:49:44 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
2017-12-22 07:31:00 +03:00
|
|
|
mc->init = xtfpga_lx200_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2017-10-05 16:51:00 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 96 * MiB;
|
2015-09-04 21:37:08 +03:00
|
|
|
}
|
2014-02-02 02:44:41 +04:00
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static const TypeInfo xtfpga_lx200_type = {
|
2015-09-19 11:49:44 +03:00
|
|
|
.name = MACHINE_TYPE_NAME("lx200"),
|
|
|
|
.parent = TYPE_MACHINE,
|
2017-12-22 07:31:00 +03:00
|
|
|
.class_init = xtfpga_lx200_class_init,
|
2015-09-19 11:49:44 +03:00
|
|
|
};
|
2015-09-04 21:37:08 +03:00
|
|
|
|
2015-09-24 16:18:51 +03:00
|
|
|
static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
2015-09-24 16:18:51 +03:00
|
|
|
mc->init = xtfpga_lx200_nommu_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 96 * MiB;
|
2015-09-24 16:18:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xtfpga_lx200_nommu_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("lx200-nommu"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = xtfpga_lx200_nommu_class_init,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
|
2015-09-04 21:37:08 +03:00
|
|
|
{
|
2015-09-19 11:49:44 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
2017-12-22 07:31:00 +03:00
|
|
|
mc->init = xtfpga_ml605_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2017-10-05 16:51:00 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
|
2015-09-04 21:37:08 +03:00
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static const TypeInfo xtfpga_ml605_type = {
|
2015-09-19 11:49:44 +03:00
|
|
|
.name = MACHINE_TYPE_NAME("ml605"),
|
|
|
|
.parent = TYPE_MACHINE,
|
2017-12-22 07:31:00 +03:00
|
|
|
.class_init = xtfpga_ml605_class_init,
|
2015-09-19 11:49:44 +03:00
|
|
|
};
|
2014-02-02 02:44:41 +04:00
|
|
|
|
2015-09-24 16:18:51 +03:00
|
|
|
static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
2015-09-24 16:18:51 +03:00
|
|
|
mc->init = xtfpga_ml605_nommu_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 256 * MiB;
|
2015-09-24 16:18:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xtfpga_ml605_nommu_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("ml605-nommu"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = xtfpga_ml605_nommu_class_init,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
|
2011-10-16 02:56:46 +04:00
|
|
|
{
|
2015-09-19 11:49:44 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
2017-12-22 07:31:00 +03:00
|
|
|
mc->init = xtfpga_kc705_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2017-10-05 16:51:00 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
|
2011-10-16 02:56:46 +04:00
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static const TypeInfo xtfpga_kc705_type = {
|
2015-09-19 11:49:44 +03:00
|
|
|
.name = MACHINE_TYPE_NAME("kc705"),
|
|
|
|
.parent = TYPE_MACHINE,
|
2017-12-22 07:31:00 +03:00
|
|
|
.class_init = xtfpga_kc705_class_init,
|
2015-09-19 11:49:44 +03:00
|
|
|
};
|
|
|
|
|
2015-09-24 16:18:51 +03:00
|
|
|
static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
2015-09-24 16:18:51 +03:00
|
|
|
mc->init = xtfpga_kc705_nommu_init;
|
2019-01-28 02:13:34 +03:00
|
|
|
mc->max_cpus = 32;
|
2018-01-11 23:56:45 +03:00
|
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
2018-11-20 23:31:24 +03:00
|
|
|
mc->default_ram_size = 256 * MiB;
|
2015-09-24 16:18:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xtfpga_kc705_nommu_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("kc705-nommu"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = xtfpga_kc705_nommu_class_init,
|
|
|
|
};
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
static void xtfpga_machines_init(void)
|
2015-09-19 11:49:44 +03:00
|
|
|
{
|
2017-12-22 07:31:00 +03:00
|
|
|
type_register_static(&xtfpga_lx60_type);
|
|
|
|
type_register_static(&xtfpga_lx200_type);
|
|
|
|
type_register_static(&xtfpga_ml605_type);
|
|
|
|
type_register_static(&xtfpga_kc705_type);
|
2015-09-24 16:18:51 +03:00
|
|
|
type_register_static(&xtfpga_lx60_nommu_type);
|
|
|
|
type_register_static(&xtfpga_lx200_nommu_type);
|
|
|
|
type_register_static(&xtfpga_ml605_nommu_type);
|
|
|
|
type_register_static(&xtfpga_kc705_nommu_type);
|
2015-09-19 11:49:44 +03:00
|
|
|
}
|
|
|
|
|
2017-12-22 07:31:00 +03:00
|
|
|
type_init(xtfpga_machines_init)
|