2010-03-29 23:23:52 +04:00
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#ifndef QEMU_ARCH_INIT_H
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#define QEMU_ARCH_INIT_H
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2012-08-15 07:17:36 +04:00
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2010-03-29 23:23:52 +04:00
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enum {
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QEMU_ARCH_ALL = -1,
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2014-09-21 15:07:21 +04:00
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QEMU_ARCH_ALPHA = (1 << 0),
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QEMU_ARCH_ARM = (1 << 1),
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QEMU_ARCH_CRIS = (1 << 2),
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QEMU_ARCH_I386 = (1 << 3),
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QEMU_ARCH_M68K = (1 << 4),
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QEMU_ARCH_MICROBLAZE = (1 << 6),
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QEMU_ARCH_MIPS = (1 << 7),
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QEMU_ARCH_PPC = (1 << 8),
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QEMU_ARCH_S390X = (1 << 9),
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QEMU_ARCH_SH4 = (1 << 10),
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QEMU_ARCH_SPARC = (1 << 11),
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QEMU_ARCH_XTENSA = (1 << 12),
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QEMU_ARCH_OPENRISC = (1 << 13),
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QEMU_ARCH_TRICORE = (1 << 16),
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2017-01-19 01:01:46 +03:00
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QEMU_ARCH_NIOS2 = (1 << 17),
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2017-10-01 23:11:45 +03:00
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QEMU_ARCH_HPPA = (1 << 18),
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2018-03-02 15:32:59 +03:00
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QEMU_ARCH_RISCV = (1 << 19),
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2019-01-21 16:18:59 +03:00
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QEMU_ARCH_RX = (1 << 20),
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2020-01-24 03:51:21 +03:00
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QEMU_ARCH_AVR = (1 << 21),
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2020-02-24 17:29:50 +03:00
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QEMU_ARCH_NONE = (1 << 31),
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2010-03-29 23:23:52 +04:00
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};
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extern const uint32_t arch_type;
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int kvm_available(void);
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int xen_available(void);
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2021-03-23 19:53:02 +03:00
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/* default virtio transport per architecture */
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#define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \
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QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
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QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \
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QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
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QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
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#define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
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2021-03-23 19:53:03 +03:00
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#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)
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2021-03-23 19:53:02 +03:00
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2010-03-29 23:23:52 +04:00
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#endif
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