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qemu/tests/tcg/xtensa/Makefile

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tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
-include ../../../config-host.mak
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
CORE=dc232b
CROSS=xtensa-$(CORE)-elf-
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
ifndef XT
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
SIM = ../../../xtensa-softmmu/qemu-system-xtensa
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting $(EXTFLAGS) -kernel
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
SIMDEBUG = -s -S
else
SIM = xt-run
SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
SIMDEBUG = --gdbserve=0
endif
target-xtensa: tests: pre-process tests linker script Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-09-18 08:13:09 +04:00
HOST_CC = gcc
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
CC = $(CROSS)gcc
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
AS = $(CROSS)gcc -x assembler-with-cpp
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
LD = $(CROSS)ld
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
target-xtensa: tests: pre-process tests linker script Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-09-18 08:13:09 +04:00
LDFLAGS = -Tlinker.ld
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
CRT = crt.o vectors.o
TESTCASES += test_b.tst
TESTCASES += test_bi.tst
#TESTCASES += test_boolean.tst
target-xtensa: add breakpoint tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-01-13 09:22:07 +04:00
TESTCASES += test_break.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_bz.tst
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
TESTCASES += test_cache.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_clamps.tst
target-xtensa: add extui unit test Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-12-17 00:32:27 +04:00
TESTCASES += test_extui.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_fail.tst
TESTCASES += test_interrupt.tst
TESTCASES += test_loop.tst
target-xtensa: add MAC16 unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:41 +04:00
TESTCASES += test_mac16.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_max.tst
TESTCASES += test_min.tst
TESTCASES += test_mmu.tst
TESTCASES += test_mul16.tst
TESTCASES += test_mul32.tst
TESTCASES += test_nsa.tst
ifdef XT
TESTCASES += test_pipeline.tst
endif
TESTCASES += test_quo.tst
TESTCASES += test_rem.tst
TESTCASES += test_rst0.tst
target-xtensa: add s32c1i unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-05 07:15:26 +04:00
TESTCASES += test_s32c1i.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_sar.tst
TESTCASES += test_sext.tst
TESTCASES += test_shift.tst
target-xtensa: add SR accessibility unit tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-05 07:15:25 +04:00
TESTCASES += test_sr.tst
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
TESTCASES += test_timer.tst
TESTCASES += test_windowed.tst
all: build
target-xtensa: tests: pre-process tests linker script Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-09-18 08:13:09 +04:00
linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
$(HOST_CC) $(XTENSA_INC) -E -P $< -o $@
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
%.o: $(XTENSA_SRC_PATH)/%.c
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
tests/tcg/xtensa: Fix out-of-tree build Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-06 22:41:37 +04:00
%.o: $(XTENSA_SRC_PATH)/%.S
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
$(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target-xtensa: tests: pre-process tests linker script Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-09-18 08:13:09 +04:00
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
build: $(TESTCASES)
check: $(addprefix run-, $(TESTCASES))
run-%.tst: %.tst
$(SIM) $(SIMFLAGS) ./$<
run-test_fail.tst: test_fail.tst
! $(SIM) $(SIMFLAGS) ./$<
debug-%.tst: %.tst
$(SIM) $(SIMDEBUG) $(SIMFLAGS) ./$<
target-xtensa: improve unit tests debugging - add testcase announcement; - add global symbols for individual tests; - add host-debug-* makefile target. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-03-16 01:24:57 +04:00
host-debug-%.tst: %.tst
gdb --args $(SIM) $(SIMFLAGS) ./$<
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
clean:
target-xtensa: tests: pre-process tests linker script Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-09-18 08:13:09 +04:00
$(RM) -fr $(TESTCASES) $(CRT) linker.ld
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