2023-05-12 17:40:48 +03:00
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# AArch64 A64 allowed instruction decoding
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#
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# Copyright (c) 2023 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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2023-05-12 17:40:50 +03:00
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2023-05-12 17:41:03 +03:00
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&r rn
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2023-05-12 17:40:50 +03:00
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&ri rd imm
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2023-05-12 17:40:52 +03:00
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&rri_sf rd rn imm sf
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2023-05-12 17:40:59 +03:00
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&i imm
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2023-05-12 17:40:50 +03:00
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### Data Processing - Immediate
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# PC-rel addressing
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%imm_pcrel 5:s19 29:2
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@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel
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ADR 0 .. 10000 ................... ..... @pcrel
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ADRP 1 .. 10000 ................... ..... @pcrel
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2023-05-12 17:40:52 +03:00
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# Add/subtract (immediate)
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%imm12_sh12 10:12 !function=shl_12
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@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5
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@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12
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ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm
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ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12
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ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm
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ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12
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SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
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SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
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SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
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SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
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2023-05-12 17:40:53 +03:00
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# Add/subtract (immediate with tags)
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&rri_tag rd rn uimm6 uimm4
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@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
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ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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2023-05-12 17:40:55 +03:00
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# Logical (immediate)
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&rri_log rd rn sf dbm
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@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
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@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
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2023-05-12 17:40:56 +03:00
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# Move wide (immediate)
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&movw rd sf imm hw
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@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
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@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
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MOVN . 00 100101 .. ................ ..... @movw_64
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MOVN . 00 100101 .. ................ ..... @movw_32
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MOVZ . 10 100101 .. ................ ..... @movw_64
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MOVZ . 10 100101 .. ................ ..... @movw_32
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MOVK . 11 100101 .. ................ ..... @movw_64
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MOVK . 11 100101 .. ................ ..... @movw_32
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2023-05-12 17:40:57 +03:00
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# Bitfield
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&bitfield rd rn sf immr imms
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@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1
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@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
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2023-05-12 17:40:58 +03:00
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# Extract
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&extract rd rn rm imm sf
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EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
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EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
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2023-05-12 17:40:59 +03:00
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# Branches
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%imm26 0:s26 !function=times_4
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@branch . ..... .......................... &i imm=%imm26
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B 0 00101 .......................... @branch
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BL 1 00101 .......................... @branch
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2023-05-12 17:41:00 +03:00
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%imm19 5:s19 !function=times_4
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&cbz rt imm sf nz
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CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
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2023-05-12 17:41:01 +03:00
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%imm14 5:s14 !function=times_4
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%imm31_19 31:1 19:5
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&tbz rt imm nz bitpos
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TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
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2023-05-12 17:41:02 +03:00
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B_cond 0101010 0 ................... 0 cond:4 imm=%imm19
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2023-05-12 17:41:03 +03:00
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BR 1101011 0000 11111 000000 rn:5 00000 &r
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BLR 1101011 0001 11111 000000 rn:5 00000 &r
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RET 1101011 0010 11111 000000 rn:5 00000 &r
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2023-05-12 17:41:04 +03:00
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&braz rn m
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BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
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BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
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&reta m
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RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
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2023-05-12 17:41:05 +03:00
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&bra rn rm m
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BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
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BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
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2023-05-12 17:41:06 +03:00
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ERET 1101011 0100 11111 000000 11111 00000
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ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
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# We don't need to decode DRPS because it always UNDEFs except when
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# the processor is in halting debug state (which we don't implement).
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# The pattern is listed here as documentation.
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# DRPS 1101011 0101 11111 000000 11111 00000
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2023-06-19 13:20:19 +03:00
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# Hint instruction group
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{
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[
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YIELD 1101 0101 0000 0011 0010 0000 001 11111
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WFE 1101 0101 0000 0011 0010 0000 010 11111
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WFI 1101 0101 0000 0011 0010 0000 011 11111
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# We implement WFE to never block, so our SEV/SEVL are NOPs
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# SEV 1101 0101 0000 0011 0010 0000 100 11111
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# SEVL 1101 0101 0000 0011 0010 0000 101 11111
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# Our DGL is a NOP because we don't merge memory accesses anyway.
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# DGL 1101 0101 0000 0011 0010 0000 110 11111
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XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
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PACIA1716 1101 0101 0000 0011 0010 0001 000 11111
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PACIB1716 1101 0101 0000 0011 0010 0001 010 11111
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AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111
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AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111
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ESB 1101 0101 0000 0011 0010 0010 000 11111
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PACIAZ 1101 0101 0000 0011 0010 0011 000 11111
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PACIASP 1101 0101 0000 0011 0010 0011 001 11111
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PACIBZ 1101 0101 0000 0011 0010 0011 010 11111
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PACIBSP 1101 0101 0000 0011 0010 0011 011 11111
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AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111
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AUTIASP 1101 0101 0000 0011 0010 0011 101 11111
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AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111
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AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111
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]
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# The canonical NOP has CRm == op2 == 0, but all of the space
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# that isn't specifically allocated to an instruction must NOP
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NOP 1101 0101 0000 0011 0010 ---- --- 11111
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}
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2023-06-19 13:20:20 +03:00
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# Barriers
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CLREX 1101 0101 0000 0011 0011 ---- 010 11111
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DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
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ISB 1101 0101 0000 0011 0011 ---- 110 11111
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SB 1101 0101 0000 0011 0011 0000 111 11111
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2023-06-19 13:20:20 +03:00
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# PSTATE
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CFINV 1101 0101 0000 0 000 0100 0000 000 11111
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XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
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AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
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2023-06-19 13:20:20 +03:00
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# These are architecturally all "MSR (immediate)"; we decode the destination
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# register too because there is no commonality in our implementation.
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@msr_i .... .... .... . ... .... imm:4 ... .....
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MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
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MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
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MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
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MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
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MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
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MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
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MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
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MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
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MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
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2023-06-19 13:20:20 +03:00
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# MRS, MSR (register), SYS, SYSL. These are all essentially the
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# same instruction as far as QEMU is concerned.
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# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
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# to hand-decode it.
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SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
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SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
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SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
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2023-06-19 13:20:21 +03:00
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# Exception generation
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@i16 .... .... ... imm:16 ... .. &i
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SVC 1101 0100 000 ................ 000 01 @i16
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HVC 1101 0100 000 ................ 000 10 @i16
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SMC 1101 0100 000 ................ 000 11 @i16
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BRK 1101 0100 001 ................ 000 00 @i16
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HLT 1101 0100 010 ................ 000 00 @i16
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# These insns always UNDEF unless in halting debug state, which
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# we don't implement. So we don't need to decode them. The patterns
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# are listed here as documentation.
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# DCPS1 1101 0100 101 ................ 000 01 @i16
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# DCPS2 1101 0100 101 ................ 000 10 @i16
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# DCPS3 1101 0100 101 ................ 000 11 @i16
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target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.
The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
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# Loads and stores
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&stxr rn rt rt2 rs sz lasr
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&stlr rn rt sz lasr
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@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
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@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
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target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
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%imm1_30_p2 30:1 !function=plus_2
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@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
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target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.
The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
|
|
|
STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
|
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LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
|
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STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
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|
LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
|
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
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STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP
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LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
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# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine
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# acquire/release semantics because QEMU's cmpxchg always has those)
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CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
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# CAS, CASA, CASAL, CASL
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CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
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2023-06-19 13:20:21 +03:00
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&ldlit rt imm sz sign
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@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
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LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
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LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
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LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
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LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
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LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
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LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
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# PRFM
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NOP 11 011 0 00 ------------------- -----
|
2023-06-19 13:20:22 +03:00
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&ldstpair rt2 rt rn imm sz sign w p
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@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
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# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
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# so we ignore hints about data access patterns, and handle these like
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# plain signed offset.
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STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
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LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
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STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
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LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
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STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
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LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
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STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
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LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
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STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
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LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
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# STP and LDP: post-indexed
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STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
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LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
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LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1
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STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
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LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
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STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
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LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
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STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
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LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
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STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
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LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
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|
# STP and LDP: offset
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|
STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
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LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
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LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0
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STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
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|
LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
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STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
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|
LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
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|
STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
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|
|
LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
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|
STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
|
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|
LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
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|
|
|
|
# STP and LDP: pre-indexed
|
|
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|
|
STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
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|
LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
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|
LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1
|
|
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|
|
STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
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|
|
LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
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|
|
STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
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|
|
LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
|
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|
|
STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
|
|
|
|
LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
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|
STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
|
|
|
|
|
LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
|
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|
|
|
|
|
|
|
# STGP: store tag and pair
|
|
|
|
|
STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
2023-06-19 13:20:22 +03:00
|
|
|
|
|
|
|
|
# Load/store register (unscaled immediate)
|
|
|
|
|
&ldst_imm rt rn imm sz sign w p unpriv ext
|
|
|
|
|
@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0
|
|
|
|
|
@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1
|
|
|
|
|
@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1
|
|
|
|
|
@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
# PRFM : prefetch memory: a no-op for QEMU
|
|
|
|
|
NOP 11 111 0 00 10 0 --------- 00 ----- -----
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
|
2023-06-19 13:20:22 +03:00
|
|
|
|
|
|
|
|
# Load/store with an unsigned 12 bit immediate, which is scaled by the
|
|
|
|
|
# element size. The function gets the sz:imm and returns the scaled immediate.
|
|
|
|
|
%uimm_scaled 10:12 sz:3 !function=uimm_scaled
|
|
|
|
|
|
|
|
|
|
@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
# PRFM
|
|
|
|
|
NOP 11 111 0 01 10 ------------ ----- -----
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
# Load/store with register offset
|
|
|
|
|
&ldst rm rn rt sign ext sz opt s
|
|
|
|
|
@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst
|
|
|
|
|
STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
|
|
|
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LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0
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LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1
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LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2
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LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3
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LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0
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LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1
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LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2
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LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0
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LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1
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# PRFM
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NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----
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STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
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STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
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LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
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LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
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