2016-06-06 18:59:29 +03:00
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/*
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* ASPEED AST2400 I2C Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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2019-08-12 08:23:31 +03:00
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2016-06-06 18:59:29 +03:00
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#ifndef ASPEED_I2C_H
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#define ASPEED_I2C_H
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#include "hw/i2c/i2c.h"
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2019-08-12 08:23:31 +03:00
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#include "hw/sysbus.h"
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2022-06-13 15:05:48 +03:00
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#include "hw/registerfields.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2016-06-06 18:59:29 +03:00
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#define TYPE_ASPEED_I2C "aspeed.i2c"
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2019-09-25 17:32:40 +03:00
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#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
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#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
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2019-09-25 17:32:41 +03:00
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#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
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2022-06-13 15:05:48 +03:00
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#define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030"
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2020-09-16 21:25:18 +03:00
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OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
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2016-06-06 18:59:29 +03:00
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2019-09-25 17:32:41 +03:00
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#define ASPEED_I2C_NR_BUSSES 16
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2019-11-19 17:11:55 +03:00
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#define ASPEED_I2C_MAX_POOL_SIZE 0x800
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2022-06-13 15:05:48 +03:00
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#define ASPEED_I2C_OLD_NUM_REG 11
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2022-06-13 15:05:48 +03:00
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#define ASPEED_I2C_NEW_NUM_REG 22
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2016-06-06 18:59:29 +03:00
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2023-03-31 20:30:49 +03:00
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#define A_I2CD_M_STOP_CMD BIT(5)
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#define A_I2CD_M_RX_CMD BIT(3)
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#define A_I2CD_M_TX_CMD BIT(1)
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#define A_I2CD_M_START_CMD BIT(0)
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#define A_I2CD_MASTER_EN BIT(0)
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2022-06-13 15:05:48 +03:00
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/* Tx State Machine */
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#define I2CD_TX_STATE_MASK 0xf
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#define I2CD_IDLE 0x0
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#define I2CD_MACTIVE 0x8
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#define I2CD_MSTART 0x9
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#define I2CD_MSTARTR 0xa
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#define I2CD_MSTOP 0xb
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#define I2CD_MTXD 0xc
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#define I2CD_MRXACK 0xd
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#define I2CD_MRXD 0xe
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#define I2CD_MTXACK 0xf
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#define I2CD_SWAIT 0x1
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#define I2CD_SRXD 0x4
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#define I2CD_STXACK 0x5
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#define I2CD_STXD 0x6
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#define I2CD_SRXACK 0x7
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#define I2CD_RECOVER 0x3
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/* I2C Global Register */
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REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */
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REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */
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REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */
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FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1)
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FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1)
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REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */
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/* I2C Old Mode Device (Bus) Register */
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REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */
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FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */
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SHARED_FIELD(M_SDA_LOCK_EN, 16, 1)
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SHARED_FIELD(MULTI_MASTER_DIS, 15, 1)
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SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1)
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SHARED_FIELD(MSB_STS, 9, 1)
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SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1)
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SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1)
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SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1)
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SHARED_FIELD(DEF_ADDR_EN, 5, 1)
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SHARED_FIELD(DEF_ALERT_EN, 4, 1)
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SHARED_FIELD(DEF_ARP_EN, 3, 1)
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SHARED_FIELD(DEF_GCALL_EN, 2, 1)
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SHARED_FIELD(SLAVE_EN, 1, 1)
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SHARED_FIELD(MASTER_EN, 0, 1)
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REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */
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REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */
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REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */
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REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */
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SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */
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SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1)
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SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1)
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SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1)
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SHARED_FIELD(BUS_RECOVER_DONE, 13, 1)
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SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */
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FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */
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FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */
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FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */
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FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */
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FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */
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SHARED_FIELD(SCL_TIMEOUT, 6, 1)
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SHARED_FIELD(ABNORMAL, 5, 1)
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SHARED_FIELD(NORMAL_STOP, 4, 1)
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SHARED_FIELD(ARBIT_LOSS, 3, 1)
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SHARED_FIELD(RX_DONE, 2, 1)
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SHARED_FIELD(TX_NAK, 1, 1)
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SHARED_FIELD(TX_ACK, 0, 1)
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REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
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SHARED_FIELD(SDA_OE, 28, 1)
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SHARED_FIELD(SDA_O, 27, 1)
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SHARED_FIELD(SCL_OE, 26, 1)
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SHARED_FIELD(SCL_O, 25, 1)
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SHARED_FIELD(TX_TIMING, 23, 2)
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SHARED_FIELD(TX_STATE, 19, 4)
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SHARED_FIELD(SCL_LINE_STS, 18, 1)
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SHARED_FIELD(SDA_LINE_STS, 17, 1)
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SHARED_FIELD(BUS_BUSY_STS, 16, 1)
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SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1)
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SHARED_FIELD(SDA_O_OUT_DIR, 14, 1)
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SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1)
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SHARED_FIELD(SCL_O_OUT_DIR, 12, 1)
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SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1)
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SHARED_FIELD(S_ALT_EN, 10, 1)
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/* Command Bits */
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SHARED_FIELD(RX_DMA_EN, 9, 1)
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SHARED_FIELD(TX_DMA_EN, 8, 1)
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SHARED_FIELD(RX_BUFF_EN, 7, 1)
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SHARED_FIELD(TX_BUFF_EN, 6, 1)
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SHARED_FIELD(M_STOP_CMD, 5, 1)
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SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1)
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SHARED_FIELD(M_RX_CMD, 3, 1)
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SHARED_FIELD(S_TX_CMD, 2, 1)
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SHARED_FIELD(M_TX_CMD, 1, 1)
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SHARED_FIELD(M_START_CMD, 0, 1)
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REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
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2022-10-24 12:20:15 +03:00
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SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
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2022-06-13 15:05:48 +03:00
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REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
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2023-08-12 09:52:28 +03:00
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SHARED_FIELD(RX_COUNT, 24, 6)
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2022-06-13 15:05:48 +03:00
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SHARED_FIELD(RX_SIZE, 16, 5)
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2023-08-12 09:52:28 +03:00
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SHARED_FIELD(TX_COUNT, 8, 5)
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2022-06-13 15:05:48 +03:00
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FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */
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2023-08-12 09:52:30 +03:00
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SHARED_FIELD(BUF_ORGANIZATION, 0, 1) /* AST2600 */
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2022-06-13 15:05:48 +03:00
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REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */
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SHARED_FIELD(RX_BUF, 8, 8)
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SHARED_FIELD(TX_BUF, 0, 8)
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REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */
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REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */
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/* I2C New Mode Device (Bus) Register */
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REG32(I2CC_FUN_CTRL, 0x0)
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FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1)
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FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1)
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FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1)
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FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2)
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/* 17:0 shared with I2CD_FUN_CTRL[17:0] */
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REG32(I2CC_AC_TIMING, 0x04)
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REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08)
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/* 31:16 shared with I2CD_CMD[31:16] */
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/* 15:0 shared with I2CD_BYTE_BUF[15:0] */
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REG32(I2CC_POOL_CTRL, 0x0c)
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/* 31:0 shared with I2CD_POOL_CTRL[31:0] */
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REG32(I2CM_INTR_CTRL, 0x10)
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REG32(I2CM_INTR_STS, 0x14)
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FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4)
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FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1)
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FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1)
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FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1)
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FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1)
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/* 14:0 shared with I2CD_INTR_STS[14:0] */
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REG32(I2CM_CMD, 0x18)
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FIELD(I2CM_CMD, W1_CTRL, 31, 1)
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FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7)
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FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3)
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FIELD(I2CM_CMD, PKT_OP_EN, 16, 1)
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/* 15:0 shared with I2CD_CMD[15:0] */
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REG32(I2CM_DMA_LEN, 0x1c)
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FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
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FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11)
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FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
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FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11)
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REG32(I2CS_INTR_CTRL, 0x20)
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hw/i2c/aspeed: Add new-registers DMA slave mode RX support
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.
This is particularly useful for testing IPMB exchanges between Zephyr
and external devices, which requires multi-master I2C support and DMA in
the new register mode, because the Zephyr drivers from Aspeed use DMA in
the new mode by default. The Zephyr drivers are also using packet mode.
The typical sequence of events for receiving data in DMA slave + packet
mode is that the Zephyr firmware will configure the slave address
register with an address to receive on and configure the bus's function
control register to enable master mode and slave mode simultaneously at
startup, before any transfers are initiated.
RX DMA is enabled in the slave mode command register, and the slave RX
DMA buffer address and slave RX DMA buffer length are set. TX DMA is not
covered in this patch.
When the Aspeed I2C controller receives data from some other I2C master,
it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer
incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR
address counter and decrementing the I2CC_DMA_LEN counter. It will also
update the I2CS_DMA_LEN RX_LEN value along the way.
Once all the data has been received, the bus controller will raise an
interrupt indicating a packet command was completed, the slave address
matched, a normal stop condition was seen, and the transfer was an RX
operation.
If the master sent a NACK instead of a normal stop condition, or the
transfer timed out, then a slightly different set of interrupt status
values would be set. Those conditions are not handled in this commit.
The Zephyr firmware then collects data from the RX DMA buffer and clears
the status register by writing the PKT_MODE_EN bit to the status
register. In packet mode, clearing the packet mode interrupt enable bit
also clears most of the other interrupt bits automatically (except for a
few bits above it).
Note: if the master transmit or receive functions were in use
simultaneously with the slave mode receive functionality, then the
master mode functions may have raised the interrupt line for the bus
before the DMA slave transfer is complete. It's important to have the
slave's interrupt status register clear throughout the receive
operation, and if the slave attempts to raise the interrupt before the
master interrupt status is cleared, then it needs to re-raise the
interrupt once the master interrupt status is cleared. (And vice-versa).
That's why in this commit, when the master interrupt status is cleared
and the interrupt line is lowered, we call the slave interrupt _raise_
function, to see if the interrupt was pending. (And again, vice-versa).
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-8-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30 10:21:14 +03:00
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FIELD(I2CS_INTR_CTRL, PKT_CMD_FAIL, 17, 1)
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FIELD(I2CS_INTR_CTRL, PKT_CMD_DONE, 16, 1)
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2022-06-13 15:05:48 +03:00
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REG32(I2CS_INTR_STS, 0x24)
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/* 31:29 shared with I2CD_INTR_STS[31:29] */
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FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2)
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FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1)
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FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1)
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FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1)
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FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2)
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FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1)
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FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1)
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/* 14:0 shared with I2CD_INTR_STS[14:0] */
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hw/i2c/aspeed: Add new-registers DMA slave mode RX support
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.
This is particularly useful for testing IPMB exchanges between Zephyr
and external devices, which requires multi-master I2C support and DMA in
the new register mode, because the Zephyr drivers from Aspeed use DMA in
the new mode by default. The Zephyr drivers are also using packet mode.
The typical sequence of events for receiving data in DMA slave + packet
mode is that the Zephyr firmware will configure the slave address
register with an address to receive on and configure the bus's function
control register to enable master mode and slave mode simultaneously at
startup, before any transfers are initiated.
RX DMA is enabled in the slave mode command register, and the slave RX
DMA buffer address and slave RX DMA buffer length are set. TX DMA is not
covered in this patch.
When the Aspeed I2C controller receives data from some other I2C master,
it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer
incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR
address counter and decrementing the I2CC_DMA_LEN counter. It will also
update the I2CS_DMA_LEN RX_LEN value along the way.
Once all the data has been received, the bus controller will raise an
interrupt indicating a packet command was completed, the slave address
matched, a normal stop condition was seen, and the transfer was an RX
operation.
If the master sent a NACK instead of a normal stop condition, or the
transfer timed out, then a slightly different set of interrupt status
values would be set. Those conditions are not handled in this commit.
The Zephyr firmware then collects data from the RX DMA buffer and clears
the status register by writing the PKT_MODE_EN bit to the status
register. In packet mode, clearing the packet mode interrupt enable bit
also clears most of the other interrupt bits automatically (except for a
few bits above it).
Note: if the master transmit or receive functions were in use
simultaneously with the slave mode receive functionality, then the
master mode functions may have raised the interrupt line for the bus
before the DMA slave transfer is complete. It's important to have the
slave's interrupt status register clear throughout the receive
operation, and if the slave attempts to raise the interrupt before the
master interrupt status is cleared, then it needs to re-raise the
interrupt once the master interrupt status is cleared. (And vice-versa).
That's why in this commit, when the master interrupt status is cleared
and the interrupt line is lowered, we call the slave interrupt _raise_
function, to see if the interrupt was pending. (And again, vice-versa).
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-8-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30 10:21:14 +03:00
|
|
|
FIELD(I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1)
|
2022-06-13 15:05:48 +03:00
|
|
|
REG32(I2CS_CMD, 0x28)
|
|
|
|
|
FIELD(I2CS_CMD, W1_CTRL, 31, 1)
|
|
|
|
|
FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2)
|
|
|
|
|
FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1)
|
|
|
|
|
FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1)
|
|
|
|
|
FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1)
|
|
|
|
|
/* 13:0 shared with I2CD_CMD[13:0] */
|
|
|
|
|
REG32(I2CS_DMA_LEN, 0x2c)
|
|
|
|
|
FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
|
|
|
|
|
FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11)
|
|
|
|
|
FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
|
|
|
|
|
FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11)
|
|
|
|
|
REG32(I2CM_DMA_TX_ADDR, 0x30)
|
|
|
|
|
FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31)
|
|
|
|
|
REG32(I2CM_DMA_RX_ADDR, 0x34)
|
|
|
|
|
FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31)
|
|
|
|
|
REG32(I2CS_DMA_TX_ADDR, 0x38)
|
|
|
|
|
FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31)
|
|
|
|
|
REG32(I2CS_DMA_RX_ADDR, 0x3c)
|
|
|
|
|
FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31)
|
|
|
|
|
REG32(I2CS_DEV_ADDR, 0x40)
|
|
|
|
|
REG32(I2CM_DMA_LEN_STS, 0x48)
|
|
|
|
|
FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13)
|
|
|
|
|
FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13)
|
|
|
|
|
REG32(I2CS_DMA_LEN_STS, 0x4c)
|
|
|
|
|
FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13)
|
|
|
|
|
FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13)
|
|
|
|
|
REG32(I2CC_DMA_ADDR, 0x50)
|
|
|
|
|
REG32(I2CC_DMA_LEN, 0x54)
|
|
|
|
|
|
2016-06-06 18:59:29 +03:00
|
|
|
struct AspeedI2CState;
|
|
|
|
|
|
2021-10-12 09:20:08 +03:00
|
|
|
#define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus"
|
|
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS)
|
|
|
|
|
struct AspeedI2CBus {
|
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
|
2016-06-06 18:59:29 +03:00
|
|
|
struct AspeedI2CState *controller;
|
|
|
|
|
|
2022-06-30 10:21:14 +03:00
|
|
|
/* slave mode */
|
|
|
|
|
I2CSlave *slave;
|
|
|
|
|
|
2016-06-06 18:59:29 +03:00
|
|
|
MemoryRegion mr;
|
|
|
|
|
|
|
|
|
|
I2CBus *bus;
|
|
|
|
|
uint8_t id;
|
2019-09-25 17:32:41 +03:00
|
|
|
qemu_irq irq;
|
2016-06-06 18:59:29 +03:00
|
|
|
|
2022-06-13 15:05:48 +03:00
|
|
|
uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
|
2021-10-12 09:20:08 +03:00
|
|
|
};
|
2016-06-06 18:59:29 +03:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct AspeedI2CState {
|
2016-06-06 18:59:29 +03:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
|
|
|
|
|
MemoryRegion iomem;
|
|
|
|
|
qemu_irq irq;
|
|
|
|
|
|
|
|
|
|
uint32_t intr_status;
|
2019-11-19 17:11:56 +03:00
|
|
|
uint32_t ctrl_global;
|
2022-06-13 15:05:48 +03:00
|
|
|
uint32_t new_clk_divider;
|
2019-11-19 17:11:55 +03:00
|
|
|
MemoryRegion pool_iomem;
|
|
|
|
|
uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
|
2016-06-06 18:59:29 +03:00
|
|
|
|
|
|
|
|
AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
|
2019-11-19 17:11:58 +03:00
|
|
|
MemoryRegion *dram_mr;
|
|
|
|
|
AddressSpace dram_as;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2016-06-06 18:59:29 +03:00
|
|
|
|
2022-06-30 10:21:14 +03:00
|
|
|
#define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave"
|
|
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBusSlave, ASPEED_I2C_BUS_SLAVE)
|
|
|
|
|
struct AspeedI2CBusSlave {
|
|
|
|
|
I2CSlave i2c;
|
|
|
|
|
};
|
2019-09-25 17:32:40 +03:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct AspeedI2CClass {
|
2019-09-25 17:32:40 +03:00
|
|
|
SysBusDeviceClass parent_class;
|
|
|
|
|
|
|
|
|
|
uint8_t num_busses;
|
|
|
|
|
uint8_t reg_size;
|
|
|
|
|
uint8_t gap;
|
2019-09-25 17:32:41 +03:00
|
|
|
qemu_irq (*bus_get_irq)(AspeedI2CBus *);
|
2019-11-19 17:11:55 +03:00
|
|
|
|
|
|
|
|
uint64_t pool_size;
|
|
|
|
|
hwaddr pool_base;
|
|
|
|
|
uint8_t *(*bus_pool_base)(AspeedI2CBus *);
|
2019-11-19 17:11:56 +03:00
|
|
|
bool check_sram;
|
2019-11-19 17:11:58 +03:00
|
|
|
bool has_dma;
|
2024-07-18 09:49:13 +03:00
|
|
|
uint64_t mem_size;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2019-09-25 17:32:40 +03:00
|
|
|
|
2022-06-13 15:05:48 +03:00
|
|
|
static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)
|
|
|
|
|
{
|
|
|
|
|
return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN);
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CC_FUN_CTRL;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_FUN_CTRL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CM_CMD;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_CMD;
|
|
|
|
|
}
|
|
|
|
|
|
2022-06-13 15:05:48 +03:00
|
|
|
static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CS_DEV_ADDR;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_DEV_ADDR;
|
|
|
|
|
}
|
|
|
|
|
|
2022-06-13 15:05:48 +03:00
|
|
|
static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CM_INTR_CTRL;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_INTR_CTRL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CM_INTR_STS;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_INTR_STS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CC_POOL_CTRL;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_POOL_CTRL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CC_MS_TXRX_BYTE_BUF;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_BYTE_BUF;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CC_DMA_LEN;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_DMA_LEN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
if (aspeed_i2c_is_new_mode(bus->controller)) {
|
|
|
|
|
return R_I2CC_DMA_ADDR;
|
|
|
|
|
}
|
|
|
|
|
return R_I2CD_DMA_ADDR;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus),
|
|
|
|
|
MASTER_EN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
|
|
|
|
|
{
|
|
|
|
|
uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus);
|
|
|
|
|
return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) ||
|
|
|
|
|
SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN);
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-06 01:41:50 +03:00
|
|
|
I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
|
2016-06-06 18:59:29 +03:00
|
|
|
|
|
|
|
|
#endif /* ASPEED_I2C_H */
|