2012-04-12 04:17:53 +04:00
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/*
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* QEMU MicroBlaze CPU
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*
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2012-04-12 04:26:28 +04:00
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* Copyright (c) 2009 Edgar E. Iglesias
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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2012-04-12 04:17:53 +04:00
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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2014-01-13 07:35:26 +04:00
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* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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2012-04-12 04:17:53 +04:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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2016-01-26 21:05:31 +03:00
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#include "qemu/osdep.h"
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2022-02-07 11:27:56 +03:00
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#include "qemu/log.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2012-04-12 04:17:53 +04:00
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#include "cpu.h"
|
2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2013-04-23 16:27:09 +04:00
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#include "hw/qdev-properties.h"
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2016-03-15 15:18:37 +03:00
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#include "exec/exec-all.h"
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2022-12-30 18:54:58 +03:00
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#include "exec/gdbstub.h"
|
2019-08-08 19:30:35 +03:00
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#include "fpu/softfloat-helpers.h"
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2023-02-27 16:51:55 +03:00
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#include "tcg/tcg.h"
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2012-04-12 04:17:53 +04:00
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2015-06-19 07:16:38 +03:00
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static const struct {
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const char *name;
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uint8_t version_id;
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} mb_cpu_lookup[] = {
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/* These key value are as per MBV field in PVR0 */
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1A},
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{"9.0", 0x1B},
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{"9.1", 0x1D},
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{"9.2", 0x1F},
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{"9.3", 0x20},
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2017-01-11 14:06:52 +03:00
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{"9.4", 0x21},
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{"9.5", 0x22},
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{"9.6", 0x23},
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2017-06-15 14:37:10 +03:00
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{"10.0", 0x24},
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2015-06-19 07:16:38 +03:00
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{NULL, 0},
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};
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2012-04-12 04:17:53 +04:00
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2018-04-16 23:23:05 +03:00
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/* If no specific version gets selected, default to the following. */
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#define DEFAULT_CPU_VERSION "10.0"
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2013-06-21 21:09:18 +04:00
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static void mb_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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2020-08-20 07:33:32 +03:00
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cpu->env.pc = value;
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2020-09-04 22:08:24 +03:00
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/* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
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cpu->env.iflags = 0;
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}
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2022-09-30 20:31:21 +03:00
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static vaddr mb_cpu_get_pc(CPUState *cs)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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return cpu->env.pc;
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}
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2020-10-29 22:30:01 +03:00
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static void mb_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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2020-09-04 22:08:24 +03:00
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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2023-02-27 16:51:55 +03:00
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tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
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cpu->env.pc = tb->pc;
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2020-09-04 22:08:24 +03:00
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cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
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2013-06-21 21:09:18 +04:00
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}
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2022-10-24 13:29:48 +03:00
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static void mb_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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cpu->env.pc = data[0];
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cpu->env.iflags = data[1];
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}
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2013-08-25 20:53:55 +04:00
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static bool mb_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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2014-01-13 07:35:26 +04:00
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#ifndef CONFIG_USER_ONLY
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2021-01-22 03:18:53 +03:00
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static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
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cpu->ns_axi_dp = level & en;
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}
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static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
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cpu->ns_axi_ip = level & en;
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}
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static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
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cpu->ns_axi_dc = level & en;
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}
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static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
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cpu->ns_axi_ic = level & en;
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}
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2014-01-13 07:35:26 +04:00
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static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
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if (level) {
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cpu_interrupt(cs, type);
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} else {
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cpu_reset_interrupt(cs, type);
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}
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}
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#endif
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2022-11-24 14:50:12 +03:00
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static void mb_cpu_reset_hold(Object *obj)
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2012-04-12 04:17:53 +04:00
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{
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2022-11-24 14:50:12 +03:00
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CPUState *s = CPU(obj);
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2012-04-12 04:17:53 +04:00
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
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CPUMBState *env = &cpu->env;
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2022-11-24 14:50:12 +03:00
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if (mcc->parent_phases.hold) {
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mcc->parent_phases.hold(obj);
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}
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2012-04-12 04:17:53 +04:00
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2016-11-14 17:19:17 +03:00
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memset(env, 0, offsetof(CPUMBState, end_reset_fields));
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2012-06-01 07:23:28 +04:00
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env->res_addr = RES_ADDR_NONE;
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2012-04-12 04:26:28 +04:00
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/* Disable stack protector. */
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env->shr = ~0;
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2020-08-20 07:33:32 +03:00
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env->pc = cpu->cfg.base_vectors;
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2015-07-23 18:13:56 +03:00
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2015-05-29 09:30:05 +03:00
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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2020-08-18 21:58:23 +03:00
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mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
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2015-05-29 09:30:05 +03:00
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#else
|
2020-08-18 21:58:23 +03:00
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mb_cpu_write_msr(env, 0);
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2015-05-29 09:30:05 +03:00
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mmu_init(&env->mmu);
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#endif
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}
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2015-06-24 06:57:36 +03:00
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static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_microblaze;
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info->print_insn = print_insn_microblaze;
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}
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2015-05-29 09:30:05 +03:00
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
|
2015-06-19 07:16:38 +03:00
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uint8_t version_code = 0;
|
2018-04-16 23:23:05 +03:00
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const char *version;
|
2015-06-19 07:16:38 +03:00
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int i = 0;
|
2016-10-20 14:26:03 +03:00
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
|
2015-05-29 09:30:05 +03:00
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2018-04-17 19:17:40 +03:00
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if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
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error_setg(errp, "addr-size %d is out of range (32 - 64)",
|
2018-04-13 23:04:37 +03:00
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cpu->cfg.addr_size);
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return;
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}
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2015-05-29 09:30:05 +03:00
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qemu_init_vcpu(cs);
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2018-04-16 23:23:05 +03:00
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version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
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for (i = 0; mb_cpu_lookup[i].name && version; i++) {
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if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
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2015-06-19 07:16:38 +03:00
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version_code = mb_cpu_lookup[i].version_id;
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break;
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}
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}
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|
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if (!version_code) {
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qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
|
|
|
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}
|
|
|
|
|
2020-09-04 21:11:28 +03:00
|
|
|
cpu->cfg.pvr_regs[0] =
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(PVR0_USE_EXC_MASK |
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|
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PVR0_USE_ICACHE_MASK |
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PVR0_USE_DCACHE_MASK |
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|
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(cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
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|
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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|
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(cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
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|
|
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(cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
|
|
|
|
(cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
|
|
|
|
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
|
|
|
|
(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
|
|
|
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(version_code << PVR0_VERSION_SHIFT) |
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|
|
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
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|
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cpu->cfg.pvr_user1);
|
|
|
|
|
|
|
|
cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
|
|
|
|
|
|
|
|
cpu->cfg.pvr_regs[2] =
|
|
|
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(PVR2_D_OPB_MASK |
|
|
|
|
PVR2_D_LMB_MASK |
|
|
|
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PVR2_I_OPB_MASK |
|
|
|
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PVR2_I_LMB_MASK |
|
|
|
|
PVR2_FPU_EXC_MASK |
|
|
|
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(cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
|
|
|
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
|
|
|
|
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
|
|
|
|
(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
|
|
|
|
(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
|
|
|
|
(cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
|
|
|
|
(cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
|
|
|
|
(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
|
|
|
|
(cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
|
|
|
|
(cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
|
|
|
|
(cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
|
|
|
|
(cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
|
|
|
|
(cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
|
|
|
|
(cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
|
|
|
|
|
|
|
|
cpu->cfg.pvr_regs[5] |=
|
|
|
|
cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
|
|
|
|
|
|
|
|
cpu->cfg.pvr_regs[10] =
|
|
|
|
(0x0c000000 | /* Default to spartan 3a dsp family. */
|
|
|
|
(cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
|
|
|
|
|
|
|
|
cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
|
|
|
|
16 << 17);
|
2012-04-12 04:26:28 +04:00
|
|
|
|
2020-09-04 21:31:57 +03:00
|
|
|
cpu->cfg.mmu = 3;
|
|
|
|
cpu->cfg.mmu_tlb_access = 3;
|
|
|
|
cpu->cfg.mmu_zones = 16;
|
|
|
|
cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
|
|
|
|
|
2013-01-05 18:27:31 +04:00
|
|
|
mcc->parent_realize(dev, errp);
|
|
|
|
}
|
|
|
|
|
2012-04-12 04:34:40 +04:00
|
|
|
static void mb_cpu_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
|
|
|
|
CPUMBState *env = &cpu->env;
|
|
|
|
|
2022-12-30 18:54:58 +03:00
|
|
|
gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
|
|
|
|
mb_cpu_gdb_write_stack_protect, 2,
|
|
|
|
"microblaze-stack-protect.xml", 0);
|
2012-04-12 04:34:40 +04:00
|
|
|
|
|
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
|
2013-01-20 04:10:52 +04:00
|
|
|
|
2014-01-13 07:35:26 +04:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
/* Inbound IRQ and FIR lines */
|
|
|
|
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
|
2021-01-22 03:18:53 +03:00
|
|
|
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
|
|
|
|
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
|
|
|
|
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
|
|
|
|
qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
|
2014-01-13 07:35:26 +04:00
|
|
|
#endif
|
2012-04-12 04:34:40 +04:00
|
|
|
}
|
|
|
|
|
2013-04-23 16:27:09 +04:00
|
|
|
static Property mb_properties[] = {
|
2015-05-29 09:31:20 +03:00
|
|
|
DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
|
2015-05-29 09:30:43 +03:00
|
|
|
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
|
2015-05-29 09:32:35 +03:00
|
|
|
false),
|
2018-04-13 23:04:37 +03:00
|
|
|
/*
|
|
|
|
* This is the C_ADDR_SIZE synth-time configuration option of the
|
|
|
|
* MicroBlaze cores. Supported values range between 32 and 64.
|
|
|
|
*
|
|
|
|
* When set to > 32, 32bit MicroBlaze can emit load/stores
|
|
|
|
* with extended addressing.
|
|
|
|
*/
|
|
|
|
DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
|
2015-05-29 09:31:58 +03:00
|
|
|
/* If use-fpu > 0 - FPU is enabled
|
|
|
|
* If use-fpu = 2 - Floating point conversion and square root instructions
|
|
|
|
* are enabled
|
|
|
|
*/
|
2015-06-19 07:16:25 +03:00
|
|
|
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
|
2017-06-20 14:06:44 +03:00
|
|
|
/* If use-hw-mul > 0 - Multiplier is enabled
|
|
|
|
* If use-hw-mul = 2 - 64-bit multiplier is enabled
|
|
|
|
*/
|
|
|
|
DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
|
2017-06-16 18:21:05 +03:00
|
|
|
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
|
2017-06-18 10:34:36 +03:00
|
|
|
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
|
2017-06-20 14:13:26 +03:00
|
|
|
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
|
2017-06-20 14:53:53 +03:00
|
|
|
DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
|
2015-06-19 07:16:29 +03:00
|
|
|
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
|
2021-01-22 03:18:53 +03:00
|
|
|
/*
|
|
|
|
* use-non-secure enables/disables the use of the non_secure[3:0] signals.
|
|
|
|
* It is a bitfield where 1 = non-secure for the following bits and their
|
|
|
|
* corresponding interfaces:
|
|
|
|
* 0x1 - M_AXI_DP
|
|
|
|
* 0x2 - M_AXI_IP
|
|
|
|
* 0x4 - M_AXI_DC
|
|
|
|
* 0x8 - M_AXI_IC
|
|
|
|
*/
|
|
|
|
DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
|
2015-06-19 07:16:32 +03:00
|
|
|
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
|
|
|
|
false),
|
2015-06-19 07:16:35 +03:00
|
|
|
DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
|
2019-01-04 17:05:10 +03:00
|
|
|
/* Enables bus exceptions on failed data accesses (load/stores). */
|
|
|
|
DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
|
|
|
|
cfg.dopb_bus_exception, false),
|
|
|
|
/* Enables bus exceptions on failed instruction fetches. */
|
|
|
|
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
|
|
|
|
cfg.iopb_bus_exception, false),
|
2019-10-30 15:55:08 +03:00
|
|
|
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
|
|
|
|
cfg.illegal_opcode_exception, false),
|
2019-10-30 16:03:38 +03:00
|
|
|
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
|
|
|
|
cfg.div_zero_exception, false),
|
2019-10-30 16:09:37 +03:00
|
|
|
DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
|
|
|
|
cfg.unaligned_exceptions, false),
|
2019-10-30 15:49:14 +03:00
|
|
|
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
|
|
|
|
cfg.opcode_0_illegal, false),
|
2015-06-19 07:16:38 +03:00
|
|
|
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
|
2015-06-19 07:16:42 +03:00
|
|
|
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
|
2019-10-30 16:15:46 +03:00
|
|
|
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
|
2019-10-30 16:22:15 +03:00
|
|
|
DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
|
2013-04-23 16:27:09 +04:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2017-08-24 19:31:35 +03:00
|
|
|
static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
|
|
|
|
{
|
|
|
|
return object_class_by_name(TYPE_MICROBLAZE_CPU);
|
|
|
|
}
|
|
|
|
|
2021-05-17 13:51:31 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
#include "hw/core/sysemu-cpu-ops.h"
|
|
|
|
|
|
|
|
static const struct SysemuCPUOps mb_sysemu_ops = {
|
2021-05-17 13:51:37 +03:00
|
|
|
.get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
|
2021-05-17 13:51:31 +03:00
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2021-02-04 19:39:23 +03:00
|
|
|
#include "hw/core/tcg-cpu-ops.h"
|
|
|
|
|
2021-02-28 02:21:17 +03:00
|
|
|
static const struct TCGCPUOps mb_tcg_ops = {
|
2021-02-04 19:39:23 +03:00
|
|
|
.initialize = mb_tcg_init,
|
|
|
|
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
|
2022-10-24 13:29:48 +03:00
|
|
|
.restore_state_to_opc = mb_restore_state_to_opc,
|
2021-02-04 19:39:23 +03:00
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
2021-09-15 03:17:38 +03:00
|
|
|
.tlb_fill = mb_cpu_tlb_fill,
|
2021-09-11 19:54:23 +03:00
|
|
|
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
|
2021-02-04 19:39:23 +03:00
|
|
|
.do_interrupt = mb_cpu_do_interrupt,
|
|
|
|
.do_transaction_failed = mb_cpu_transaction_failed,
|
|
|
|
.do_unaligned_access = mb_cpu_do_unaligned_access,
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
};
|
|
|
|
|
2012-04-12 04:17:53 +04:00
|
|
|
static void mb_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-01-20 22:03:32 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-04-12 04:17:53 +04:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
|
2022-11-24 14:50:12 +03:00
|
|
|
ResettableClass *rc = RESETTABLE_CLASS(oc);
|
2012-04-12 04:17:53 +04:00
|
|
|
|
2018-01-14 05:04:12 +03:00
|
|
|
device_class_set_parent_realize(dc, mb_cpu_realizefn,
|
|
|
|
&mcc->parent_realize);
|
2022-11-24 14:50:12 +03:00
|
|
|
resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
|
|
|
|
&mcc->parent_phases);
|
2013-01-20 22:03:32 +04:00
|
|
|
|
2017-08-24 19:31:35 +03:00
|
|
|
cc->class_by_name = mb_cpu_class_by_name;
|
2013-08-25 20:53:55 +04:00
|
|
|
cc->has_work = mb_cpu_has_work;
|
2021-02-04 19:39:23 +03:00
|
|
|
|
2013-05-27 03:33:50 +04:00
|
|
|
cc->dump_state = mb_cpu_dump_state;
|
2013-06-21 21:09:18 +04:00
|
|
|
cc->set_pc = mb_cpu_set_pc;
|
2022-09-30 20:31:21 +03:00
|
|
|
cc->get_pc = mb_cpu_get_pc;
|
2013-06-29 06:18:45 +04:00
|
|
|
cc->gdb_read_register = mb_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = mb_cpu_gdb_write_register;
|
2021-02-04 19:39:23 +03:00
|
|
|
|
2019-04-02 12:06:02 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2013-01-20 22:03:32 +04:00
|
|
|
dc->vmsd = &vmstate_mb_cpu;
|
2021-05-17 13:51:31 +03:00
|
|
|
cc->sysemu_ops = &mb_sysemu_ops;
|
2020-09-03 07:41:00 +03:00
|
|
|
#endif
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, mb_properties);
|
2022-12-30 18:54:58 +03:00
|
|
|
cc->gdb_num_core_regs = 32 + 25;
|
|
|
|
cc->gdb_core_xml_file = "microblaze-core.xml";
|
2015-06-24 06:57:36 +03:00
|
|
|
|
|
|
|
cc->disas_set_info = mb_disas_set_info;
|
2021-02-04 19:39:23 +03:00
|
|
|
cc->tcg_ops = &mb_tcg_ops;
|
2012-04-12 04:17:53 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo mb_cpu_type_info = {
|
|
|
|
.name = TYPE_MICROBLAZE_CPU,
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
.instance_size = sizeof(MicroBlazeCPU),
|
2023-09-14 01:06:21 +03:00
|
|
|
.instance_align = __alignof(MicroBlazeCPU),
|
2012-04-12 04:34:40 +04:00
|
|
|
.instance_init = mb_cpu_initfn,
|
2012-04-12 04:17:53 +04:00
|
|
|
.class_size = sizeof(MicroBlazeCPUClass),
|
|
|
|
.class_init = mb_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mb_cpu_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mb_cpu_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mb_cpu_register_types)
|