2009-10-07 18:56:24 +04:00
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/*
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* QEMU IDE Emulation: PCI cmd646 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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/* CMD646 specific */
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define UDIDETCR0 0x73
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#define UDIDETCR1 0x7B
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static void cmd646_update_irq(PCIIDEState *d);
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static void ide_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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IDEBus *bus;
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if (region_num <= 3) {
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bus = &d->bus[(region_num >> 1)];
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if (region_num & 1) {
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register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
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register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
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} else {
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register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
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register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
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/* data ports */
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register_ioport_write(addr, 2, 2, ide_data_writew, bus);
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register_ioport_read(addr, 2, 2, ide_data_readw, bus);
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register_ioport_write(addr, 4, 4, ide_data_writel, bus);
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register_ioport_read(addr, 4, 4, ide_data_readl, bus);
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}
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}
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}
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2009-10-07 18:56:27 +04:00
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static PCIIDEState *pci_from_bm(BMDMAState *bm)
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{
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if (bm->unit == 0) {
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return container_of(bm, PCIIDEState, bmdma[0]);
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} else {
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return container_of(bm, PCIIDEState, bmdma[1]);
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}
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}
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2009-10-07 18:56:24 +04:00
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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2009-10-07 18:56:27 +04:00
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PCIIDEState *pci_dev = pci_from_bm(bm);
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2009-10-07 18:56:24 +04:00
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uint32_t val;
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 1:
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2009-10-07 18:56:25 +04:00
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val = pci_dev->dev.config[MRDMODE];
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2009-10-07 18:56:24 +04:00
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break;
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case 2:
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val = bm->status;
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break;
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case 3:
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2009-10-07 18:56:28 +04:00
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if (bm->unit == 0) {
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2009-10-07 18:56:25 +04:00
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val = pci_dev->dev.config[UDIDETCR0];
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2009-10-07 18:56:24 +04:00
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} else {
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2009-10-07 18:56:25 +04:00
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val = pci_dev->dev.config[UDIDETCR1];
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2009-10-07 18:56:24 +04:00
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}
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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2009-10-07 18:56:27 +04:00
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PCIIDEState *pci_dev = pci_from_bm(bm);
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2009-10-07 18:56:24 +04:00
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) {
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case 1:
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2009-10-07 18:56:25 +04:00
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pci_dev->dev.config[MRDMODE] =
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(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
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cmd646_update_irq(pci_dev);
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2009-10-07 18:56:24 +04:00
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break;
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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case 3:
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2009-10-07 18:56:28 +04:00
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if (bm->unit == 0)
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2009-10-07 18:56:25 +04:00
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pci_dev->dev.config[UDIDETCR0] = val;
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else
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pci_dev->dev.config[UDIDETCR1] = val;
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2009-10-07 18:56:24 +04:00
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break;
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}
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}
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static void bmdma_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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int i;
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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d->bus[i].bmdma = bm;
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bm->bus = d->bus+i;
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qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
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register_ioport_read(addr, 4, 1, bmdma_readb, bm);
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register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
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register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
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register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
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register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
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register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
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register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
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addr += 8;
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}
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}
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/* XXX: call it also when the MRDMODE is changed from the PCI config
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registers */
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static void cmd646_update_irq(PCIIDEState *d)
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{
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int pci_level;
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pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
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((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
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qemu_set_irq(d->dev.irq[0], pci_level);
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}
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level)
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{
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PCIIDEState *d = opaque;
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int irq_mask;
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irq_mask = MRDMODE_INTR_CH0 << channel;
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if (level)
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d->dev.config[MRDMODE] |= irq_mask;
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else
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d->dev.config[MRDMODE] &= ~irq_mask;
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cmd646_update_irq(d);
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}
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static void cmd646_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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unsigned int i;
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for (i = 0; i < 2; i++)
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ide_dma_cancel(&d->bmdma[i]);
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}
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/* CMD646 PCI IDE controller */
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static int pci_cmd646_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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uint8_t *pci_conf = d->dev.config;
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qemu_irq *irq;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
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pci_conf[0x08] = 0x07; // IDE controller revision
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pci_conf[0x09] = 0x8f;
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pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
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pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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pci_conf[0x51] = 0x04; // enable IDE0
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if (d->secondary) {
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/* XXX: if not enabled, really disable the seconday IDE controller */
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pci_conf[0x51] |= 0x08; /* enable IDE1 */
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}
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pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
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pci_conf[0x3d] = 0x01; // interrupt on pin 1
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irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
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ide_bus_new(&d->bus[0], &d->dev.qdev);
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ide_bus_new(&d->bus[1], &d->dev.qdev);
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ide_init2(&d->bus[0], NULL, NULL, irq[0]);
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ide_init2(&d->bus[1], NULL, NULL, irq[1]);
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2009-10-07 22:55:32 +04:00
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vmstate_register(0, &vmstate_ide_pci, d);
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2009-10-07 18:56:24 +04:00
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qemu_register_reset(cmd646_reset, d);
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cmd646_reset(d);
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return 0;
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}
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void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
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int secondary_ide_enabled)
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{
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PCIDevice *dev;
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dev = pci_create(bus, -1, "CMD646 IDE");
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qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
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qdev_init_nofail(&dev->qdev);
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pci_ide_create_devs(dev, hd_table);
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}
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static PCIDeviceInfo cmd646_ide_info[] = {
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{
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.qdev.name = "CMD646 IDE",
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.qdev.size = sizeof(PCIIDEState),
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.init = pci_cmd646_ide_initfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
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DEFINE_PROP_END_OF_LIST(),
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},
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},{
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/* end of list */
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}
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};
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static void cmd646_ide_register(void)
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{
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pci_qdev_register_many(cmd646_ide_info);
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}
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device_init(cmd646_ide_register);
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