2003-08-09 03:58:05 +04:00
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/*
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* Software MMU support
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2007-09-17 01:08:06 +04:00
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*
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2011-09-22 00:00:18 +04:00
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* Generate inline load/store functions for one MMU mode and data
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* size.
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*
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2015-01-20 18:19:34 +03:00
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* Generate a store function as well as signed and unsigned loads.
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2011-09-22 00:00:18 +04:00
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*
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2014-03-28 22:11:26 +04:00
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* Not used directly but included from cpu_ldst.h.
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2011-09-22 00:00:18 +04:00
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*
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2003-08-09 03:58:05 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-08-09 03:58:05 +04:00
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*/
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2016-06-09 20:31:47 +03:00
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#if !defined(SOFTMMU_CODE_ACCESS)
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2017-01-25 19:14:15 +03:00
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#include "trace-root.h"
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2016-06-09 20:31:47 +03:00
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#endif
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#include "trace/mem.h"
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2003-08-09 03:58:05 +04:00
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#if DATA_SIZE == 8
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#define SUFFIX q
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2003-10-28 00:22:23 +03:00
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#define USUFFIX q
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2003-08-09 03:58:05 +04:00
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#define DATA_TYPE uint64_t
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2015-07-10 12:56:50 +03:00
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#define SHIFT 3
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 4
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#define SUFFIX l
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2003-10-28 00:22:23 +03:00
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#define USUFFIX l
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2003-08-09 03:58:05 +04:00
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#define DATA_TYPE uint32_t
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2015-07-10 12:56:50 +03:00
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#define SHIFT 2
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 2
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#define SUFFIX w
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2003-10-28 00:22:23 +03:00
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#define USUFFIX uw
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2003-08-09 03:58:05 +04:00
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#define DATA_TYPE uint16_t
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#define DATA_STYPE int16_t
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2015-07-10 12:56:50 +03:00
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#define SHIFT 1
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 1
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#define SUFFIX b
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2003-10-28 00:22:23 +03:00
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#define USUFFIX ub
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2003-08-09 03:58:05 +04:00
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#define DATA_TYPE uint8_t
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#define DATA_STYPE int8_t
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2015-07-10 12:56:50 +03:00
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#define SHIFT 0
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2003-08-09 03:58:05 +04:00
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#else
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#error unsupported data size
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#endif
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#if DATA_SIZE == 8
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#define RES_TYPE uint64_t
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#else
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2010-06-02 00:12:32 +04:00
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#define RES_TYPE uint32_t
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2003-08-09 03:58:05 +04:00
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#endif
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2014-03-28 14:15:30 +04:00
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#ifdef SOFTMMU_CODE_ACCESS
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2005-11-29 00:19:04 +03:00
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#define ADDR_READ addr_code
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2014-03-28 14:18:14 +04:00
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#define MMUSUFFIX _cmmu
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2015-07-10 12:56:50 +03:00
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#define URETSUFFIX SUFFIX
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#define SRETSUFFIX SUFFIX
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2005-11-29 00:19:04 +03:00
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#else
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#define ADDR_READ addr_read
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2014-03-28 14:18:14 +04:00
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#define MMUSUFFIX _mmu
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2015-07-10 12:56:50 +03:00
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#define URETSUFFIX USUFFIX
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#define SRETSUFFIX glue(s, SUFFIX)
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2005-11-29 00:19:04 +03:00
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#endif
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2003-08-09 03:58:05 +04:00
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2004-01-04 21:15:29 +03:00
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/* generic load/store macros */
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2011-09-18 18:55:46 +04:00
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static inline RES_TYPE
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2015-07-10 12:56:50 +03:00
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glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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target_ulong ptr,
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uintptr_t retaddr)
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2003-08-09 03:58:05 +04:00
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{
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2018-10-09 20:51:25 +03:00
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CPUTLBEntry *entry;
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2003-08-09 03:58:05 +04:00
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RES_TYPE res;
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2005-01-04 02:35:10 +03:00
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target_ulong addr;
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2007-10-14 11:07:08 +04:00
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int mmu_idx;
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2015-07-10 12:56:50 +03:00
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TCGMemOpIdx oi;
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2003-10-28 00:22:23 +03:00
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2016-06-09 20:31:47 +03:00
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#if !defined(SOFTMMU_CODE_ACCESS)
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trace_guest_mem_before_exec(
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2019-03-23 02:07:18 +03:00
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env_cpu(env), ptr,
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2016-06-09 20:31:47 +03:00
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trace_mem_build_info(SHIFT, false, MO_TE, false));
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#endif
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2005-01-04 02:35:10 +03:00
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addr = ptr;
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2007-10-14 11:07:08 +04:00
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mmu_idx = CPU_MMU_INDEX;
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2018-10-09 20:51:25 +03:00
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entry = tlb_entry(env, mmu_idx, addr);
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if (unlikely(entry->ADDR_READ !=
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2008-07-03 21:57:36 +04:00
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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2015-07-10 12:56:50 +03:00
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oi = make_memop_idx(SHIFT, mmu_idx);
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res = glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr,
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oi, retaddr);
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2003-08-09 03:58:05 +04:00
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} else {
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2018-10-09 20:51:25 +03:00
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uintptr_t hostaddr = addr + entry->addend;
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2015-01-20 18:19:34 +03:00
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res = glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr);
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2003-08-09 03:58:05 +04:00
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}
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return res;
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}
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2015-07-10 12:56:50 +03:00
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static inline RES_TYPE
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glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
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{
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return glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);
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}
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2003-08-09 03:58:05 +04:00
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#if DATA_SIZE <= 2
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2011-09-18 18:55:46 +04:00
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static inline int
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2015-07-10 12:56:50 +03:00
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glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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target_ulong ptr,
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uintptr_t retaddr)
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2003-08-09 03:58:05 +04:00
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{
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2018-10-09 20:51:25 +03:00
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CPUTLBEntry *entry;
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int res;
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2005-01-04 02:35:10 +03:00
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target_ulong addr;
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2007-10-14 11:07:08 +04:00
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int mmu_idx;
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2015-07-10 12:56:50 +03:00
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TCGMemOpIdx oi;
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2003-10-28 00:22:23 +03:00
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2016-06-09 20:31:47 +03:00
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#if !defined(SOFTMMU_CODE_ACCESS)
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trace_guest_mem_before_exec(
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2019-03-23 02:07:18 +03:00
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env_cpu(env), ptr,
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2016-06-09 20:31:47 +03:00
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trace_mem_build_info(SHIFT, true, MO_TE, false));
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#endif
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2005-01-04 02:35:10 +03:00
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addr = ptr;
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2007-10-14 11:07:08 +04:00
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mmu_idx = CPU_MMU_INDEX;
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2018-10-09 20:51:25 +03:00
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entry = tlb_entry(env, mmu_idx, addr);
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if (unlikely(entry->ADDR_READ !=
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2008-07-03 21:57:36 +04:00
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
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2015-07-10 12:56:50 +03:00
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oi = make_memop_idx(SHIFT, mmu_idx);
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res = (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX),
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MMUSUFFIX)(env, addr, oi, retaddr);
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2003-08-09 03:58:05 +04:00
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} else {
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2018-10-09 20:51:25 +03:00
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uintptr_t hostaddr = addr + entry->addend;
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2015-01-20 18:19:34 +03:00
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res = glue(glue(lds, SUFFIX), _p)((uint8_t *)hostaddr);
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2003-08-09 03:58:05 +04:00
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}
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return res;
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}
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2015-07-10 12:56:50 +03:00
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static inline int
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glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
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{
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return glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);
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}
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2003-08-09 03:58:05 +04:00
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#endif
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2014-03-28 14:15:30 +04:00
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#ifndef SOFTMMU_CODE_ACCESS
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2005-11-29 00:19:04 +03:00
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2004-01-04 21:15:29 +03:00
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/* generic store macro */
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2011-09-18 18:55:46 +04:00
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static inline void
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2015-07-10 12:56:50 +03:00
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glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
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target_ulong ptr,
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RES_TYPE v, uintptr_t retaddr)
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2003-08-09 03:58:05 +04:00
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{
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2018-10-09 20:51:25 +03:00
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CPUTLBEntry *entry;
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2005-01-04 02:35:10 +03:00
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target_ulong addr;
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2007-10-14 11:07:08 +04:00
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int mmu_idx;
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2015-07-10 12:56:50 +03:00
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TCGMemOpIdx oi;
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2003-10-28 00:22:23 +03:00
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2016-06-09 20:31:47 +03:00
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#if !defined(SOFTMMU_CODE_ACCESS)
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trace_guest_mem_before_exec(
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2019-03-23 02:07:18 +03:00
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env_cpu(env), ptr,
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2016-06-09 20:31:47 +03:00
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trace_mem_build_info(SHIFT, false, MO_TE, true));
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#endif
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2005-01-04 02:35:10 +03:00
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addr = ptr;
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2007-10-14 11:07:08 +04:00
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mmu_idx = CPU_MMU_INDEX;
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2018-10-09 20:51:25 +03:00
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entry = tlb_entry(env, mmu_idx, addr);
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cputlb: read CPUTLBEntry.addr_write atomically
Updates can come from other threads, so readers that do not
take tlb_lock must use atomic_read to avoid undefined
behaviour (UB).
This completes the conversion to tlb_lock. This conversion results
on average in no performance loss, as the following experiments
(run on an Intel i7-6700K CPU @ 4.00GHz) show.
1. aarch64 bootup+shutdown test:
- Before:
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 runs):
7487.087786 task-clock (msec) # 0.998 CPUs utilized ( +- 0.12% )
31,574,905,303 cycles # 4.217 GHz ( +- 0.12% )
57,097,908,812 instructions # 1.81 insns per cycle ( +- 0.08% )
10,255,415,367 branches # 1369.747 M/sec ( +- 0.08% )
173,278,962 branch-misses # 1.69% of all branches ( +- 0.18% )
7.504481349 seconds time elapsed ( +- 0.14% )
- After:
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 runs):
7462.441328 task-clock (msec) # 0.998 CPUs utilized ( +- 0.07% )
31,478,476,520 cycles # 4.218 GHz ( +- 0.07% )
57,017,330,084 instructions # 1.81 insns per cycle ( +- 0.05% )
10,251,929,667 branches # 1373.804 M/sec ( +- 0.05% )
173,023,787 branch-misses # 1.69% of all branches ( +- 0.11% )
7.474970463 seconds time elapsed ( +- 0.07% )
2. SPEC06int:
SPEC06int (test set)
[Y axis: Speedup over master]
1.15 +-+----+------+------+------+------+------+-------+------+------+------+------+------+------+----+-+
| |
1.1 +-+.................................+++.............................+ tlb-lock-v2 (m+++x) +-+
| +++ | +++ tlb-lock-v3 (spinl|ck) |
| +++ | | +++ +++ | | |
1.05 +-+....+++...........####.........|####.+++.|......|.....###....+++...........+++....###.........+-+
| ### ++#| # |# |# ***### +++### +++#+# | +++ | #|# ### |
1 +-+++***+#++++####+++#++#++++++++++#++#+*+*++#++++#+#+****+#++++###++++###++++###++++#+#++++#+#+++-+
| *+* # #++# *** # #### *** # * *++# ****+# *| * # ****|# |# # #|# #+# # # |
0.95 +-+..*.*.#....#..#.*|*..#...#..#.*|*..#.*.*..#.*|.*.#.*++*.#.*++*+#.****.#....#+#....#.#..++#.#..+-+
| * * # # # *|* # # # *|* # * * # *++* # * * # * * # * |* # ++# # # # *** # |
| * * # ++# # *+* # # # *|* # * * # * * # * * # * * # *++* # **** # ++# # * * # |
0.9 +-+..*.*.#...|#..#.*.*..#.++#..#.*|*..#.*.*..#.*..*.#.*..*.#.*..*.#.*..*.#.*.|*.#...|#.#..*.*.#..+-+
| * * # *** # * * # |# # *+* # * * # * * # * * # * * # * * # *++* # |# # * * # |
0.85 +-+..*.*.#..*|*..#.*.*..#.***..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.*..*.#.*..*.#.****.#..*.*.#..+-+
| * * # *+* # * * # *|* # * * # * * # * * # * * # * * # * * # * * # * |* # * * # |
| * * # * * # * * # *+* # * * # * * # * * # * * # * * # * * # * * # * |* # * * # |
0.8 +-+..*.*.#..*.*..#.*.*..#.*.*..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.*..*.#.*..*.#.*++*.#..*.*.#..+-+
| * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # |
0.75 +-+--***##--***###-***###-***###-***###-***###-****##-****##-****##-****##-****##-****##--***##--+-+
400.perlben401.bzip2403.gcc429.m445.gob456.hmme45462.libqua464.h26471.omnet473483.xalancbmkgeomean
png: https://imgur.com/a/BHzpPTW
Notes:
- tlb-lock-v2 corresponds to an implementation with a mutex.
- tlb-lock-v3 corresponds to the current implementation, i.e.
a spinlock and a single lock acquisition in tlb_set_page_with_attrs.
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20181016153840.25877-1-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-16 18:38:40 +03:00
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if (unlikely(tlb_addr_write(entry) !=
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2008-07-03 21:57:36 +04:00
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(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
|
2015-07-10 12:56:50 +03:00
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oi = make_memop_idx(SHIFT, mmu_idx);
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glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi,
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retaddr);
|
2003-08-09 03:58:05 +04:00
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} else {
|
2018-10-09 20:51:25 +03:00
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uintptr_t hostaddr = addr + entry->addend;
|
2015-01-20 18:19:34 +03:00
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glue(glue(st, SUFFIX), _p)((uint8_t *)hostaddr, v);
|
2003-08-09 03:58:05 +04:00
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}
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}
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2015-07-10 12:56:50 +03:00
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static inline void
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glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
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RES_TYPE v)
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{
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glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(env, ptr, v, 0);
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}
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2014-03-28 14:15:30 +04:00
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#endif /* !SOFTMMU_CODE_ACCESS */
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2005-11-29 00:19:04 +03:00
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2003-08-09 03:58:05 +04:00
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#undef RES_TYPE
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#undef DATA_TYPE
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#undef DATA_STYPE
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#undef SUFFIX
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2003-10-28 00:22:23 +03:00
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#undef USUFFIX
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2003-08-09 03:58:05 +04:00
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#undef DATA_SIZE
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2003-10-28 00:22:23 +03:00
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#undef MMUSUFFIX
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2005-11-29 00:19:04 +03:00
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#undef ADDR_READ
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2015-07-10 12:56:50 +03:00
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#undef URETSUFFIX
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#undef SRETSUFFIX
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#undef SHIFT
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