2021-02-08 08:46:19 +03:00
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/*
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2023-03-07 05:58:19 +03:00
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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2021-02-08 08:46:19 +03:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define QEMU_GENERATE
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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2021-09-30 22:29:00 +03:00
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#include "tcg/tcg-op-gvec.h"
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2021-02-08 08:46:19 +03:00
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#include "exec/cpu_ldst.h"
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#include "exec/log.h"
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#include "internal.h"
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#include "attribs.h"
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#include "insn.h"
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#include "decode.h"
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#include "translate.h"
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#include "printinsn.h"
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2023-03-07 05:58:19 +03:00
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#include "analyze_funcs_generated.c.inc"
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typedef void (*AnalyzeInsn)(DisasContext *ctx);
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static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = {
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#define OPCODE(X) [X] = analyze_##X
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#include "opcodes_def_generated.h.inc"
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#undef OPCODE
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};
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2021-02-08 08:46:19 +03:00
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TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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TCGv hex_pred[NUM_PREGS];
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TCGv hex_this_PC;
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TCGv hex_slot_cancelled;
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TCGv hex_branch_taken;
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TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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TCGv hex_new_pred_value[NUM_PREGS];
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TCGv hex_pred_written;
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TCGv hex_store_addr[STORES_MAX];
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TCGv hex_store_width[STORES_MAX];
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TCGv hex_store_val32[STORES_MAX];
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TCGv_i64 hex_store_val64[STORES_MAX];
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TCGv hex_pkt_has_store_s1;
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TCGv hex_dczero_addr;
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TCGv hex_llsc_addr;
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TCGv hex_llsc_val;
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TCGv_i64 hex_llsc_val_i64;
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2021-09-30 22:29:00 +03:00
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TCGv hex_vstore_addr[VSTORES_MAX];
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TCGv hex_vstore_size[VSTORES_MAX];
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TCGv hex_vstore_pending[VSTORES_MAX];
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2021-02-08 08:46:19 +03:00
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static const char * const hexagon_prednames[] = {
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"p0", "p1", "p2", "p3"
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};
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2021-09-30 22:29:00 +03:00
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intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok)
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{
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intptr_t offset;
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/* See if it is already allocated */
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for (int i = 0; i < ctx->future_vregs_idx; i++) {
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if (ctx->future_vregs_num[i] == regnum) {
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return offsetof(CPUHexagonState, future_VRegs[i]);
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}
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}
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g_assert(alloc_ok);
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offset = offsetof(CPUHexagonState, future_VRegs[ctx->future_vregs_idx]);
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for (int i = 0; i < num; i++) {
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ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++;
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}
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ctx->future_vregs_idx += num;
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g_assert(ctx->future_vregs_idx <= VECTOR_TEMPS_MAX);
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return offset;
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}
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intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok)
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{
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intptr_t offset;
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/* See if it is already allocated */
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for (int i = 0; i < ctx->tmp_vregs_idx; i++) {
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if (ctx->tmp_vregs_num[i] == regnum) {
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return offsetof(CPUHexagonState, tmp_VRegs[i]);
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}
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}
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g_assert(alloc_ok);
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offset = offsetof(CPUHexagonState, tmp_VRegs[ctx->tmp_vregs_idx]);
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for (int i = 0; i < num; i++) {
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ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++;
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}
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ctx->tmp_vregs_idx += num;
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g_assert(ctx->tmp_vregs_idx <= VECTOR_TEMPS_MAX);
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return offset;
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}
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2021-04-09 04:07:33 +03:00
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static void gen_exception_raw(int excp)
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2021-02-08 08:46:19 +03:00
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{
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2021-10-03 03:47:50 +03:00
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
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2021-02-08 08:46:19 +03:00
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}
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2021-04-09 04:07:33 +03:00
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static void gen_exec_counters(DisasContext *ctx)
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{
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
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hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
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hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
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2021-09-30 22:29:00 +03:00
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT],
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hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns);
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2021-04-09 04:07:33 +03:00
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}
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2022-11-08 19:29:05 +03:00
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static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
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{
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return translator_use_goto_tb(&ctx->base, dest);
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}
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static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest)
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{
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if (use_goto_tb(ctx, dest)) {
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tcg_gen_goto_tb(idx);
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
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tcg_gen_exit_tb(ctx->base.tb, idx);
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} else {
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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2021-04-09 04:07:33 +03:00
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static void gen_end_tb(DisasContext *ctx)
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2021-02-08 08:46:19 +03:00
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{
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2022-11-10 20:49:35 +03:00
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Packet *pkt = ctx->pkt;
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2021-04-09 04:07:33 +03:00
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gen_exec_counters(ctx);
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2022-11-08 19:29:05 +03:00
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if (ctx->branch_cond != TCG_COND_NEVER) {
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if (ctx->branch_cond != TCG_COND_ALWAYS) {
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TCGLabel *skip = gen_new_label();
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tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip);
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gen_goto_tb(ctx, 0, ctx->branch_dest);
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gen_set_label(skip);
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gen_goto_tb(ctx, 1, ctx->next_PC);
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} else {
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gen_goto_tb(ctx, 0, ctx->branch_dest);
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}
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2022-11-10 20:49:35 +03:00
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} else if (ctx->is_tight_loop &&
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pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) {
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/*
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* When we're in a tight loop, we defer the endloop0 processing
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* to take advantage of direct block chaining
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*/
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TCGLabel *skip = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, skip);
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tcg_gen_subi_tl(hex_gpr[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1);
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gen_goto_tb(ctx, 0, ctx->base.tb->pc);
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gen_set_label(skip);
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gen_goto_tb(ctx, 1, ctx->next_PC);
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2022-11-08 19:29:05 +03:00
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} else {
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tcg_gen_lookup_and_goto_ptr();
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}
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2021-04-09 04:07:33 +03:00
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_end_tb(DisasContext *ctx, int excp)
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{
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gen_exec_counters(ctx);
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2022-11-08 19:29:01 +03:00
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC);
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2021-04-09 04:07:33 +03:00
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gen_exception_raw(excp);
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ctx->base.is_jmp = DISAS_NORETURN;
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2021-02-08 08:46:19 +03:00
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}
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#define PACKET_BUFFER_LEN 1028
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static void print_pkt(Packet *pkt)
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{
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GString *buf = g_string_sized_new(PACKET_BUFFER_LEN);
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snprint_a_pkt_debug(buf, pkt);
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HEX_DEBUG_LOG("%s", buf->str);
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g_string_free(buf, true);
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}
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2021-04-09 04:07:44 +03:00
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#define HEX_DEBUG_PRINT_PKT(pkt) \
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do { \
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if (HEX_DEBUG) { \
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print_pkt(pkt); \
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} \
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} while (0)
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2021-02-08 08:46:19 +03:00
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static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
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uint32_t words[])
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{
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bool found_end = false;
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int nwords, max_words;
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memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
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for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
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2021-03-15 07:53:04 +03:00
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words[nwords] =
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2021-08-10 01:32:59 +03:00
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translator_ldl(env, &ctx->base,
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ctx->base.pc_next + nwords * sizeof(uint32_t));
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2021-02-08 08:46:19 +03:00
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found_end = is_packet_end(words[nwords]);
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}
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if (!found_end) {
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/* Read too many words without finding the end */
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return 0;
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}
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/* Check for page boundary crossing */
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max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t);
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if (nwords > max_words) {
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/* We can only cross a page boundary at the beginning of a TB */
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g_assert(ctx->base.num_insns == 1);
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}
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HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
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HEX_DEBUG_LOG(" words = { ");
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for (int i = 0; i < nwords; i++) {
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HEX_DEBUG_LOG("0x%x, ", words[i]);
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}
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HEX_DEBUG_LOG("}\n");
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return nwords;
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}
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static bool check_for_attrib(Packet *pkt, int attrib)
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{
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for (int i = 0; i < pkt->num_insns; i++) {
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if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) {
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return true;
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}
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}
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return false;
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}
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static bool need_slot_cancelled(Packet *pkt)
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{
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2023-03-07 05:58:28 +03:00
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/* We only need slot_cancelled for conditional store instructions */
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Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
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for (int i = 0; i < pkt->num_insns; i++) {
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uint16_t opcode = pkt->insn[i].opcode;
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if (GET_ATTRIB(opcode, A_CONDEXEC) &&
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2023-03-07 05:58:28 +03:00
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GET_ATTRIB(opcode, A_SCALAR_STORE)) {
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Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
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return true;
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}
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}
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return false;
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2021-02-08 08:46:19 +03:00
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}
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static bool need_pred_written(Packet *pkt)
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{
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return check_for_attrib(pkt, A_WRITES_PRED_REG);
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}
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2022-11-08 19:29:01 +03:00
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static bool need_next_PC(DisasContext *ctx)
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{
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Packet *pkt = ctx->pkt;
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/* Check for conditional control flow or HW loop end */
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for (int i = 0; i < pkt->num_insns; i++) {
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uint16_t opcode = pkt->insn[i].opcode;
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if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) {
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return true;
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}
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if (GET_ATTRIB(opcode, A_HWLOOP0_END) ||
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|
|
GET_ATTRIB(opcode, A_HWLOOP1_END)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2023-03-07 05:58:19 +03:00
|
|
|
/*
|
|
|
|
* The opcode_analyze functions mark most of the writes in a packet
|
|
|
|
* However, there are some implicit writes marked as attributes
|
|
|
|
* of the applicable instructions.
|
|
|
|
*/
|
|
|
|
static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum)
|
|
|
|
{
|
|
|
|
uint16_t opcode = ctx->insn->opcode;
|
|
|
|
if (GET_ATTRIB(opcode, attrib)) {
|
|
|
|
/*
|
|
|
|
* USR is used to set overflow and FP exceptions,
|
|
|
|
* so treat it as conditional
|
|
|
|
*/
|
|
|
|
bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) ||
|
|
|
|
rnum == HEX_REG_USR;
|
|
|
|
|
|
|
|
/* LC0/LC1 is conditionally written by endloop instructions */
|
|
|
|
if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) &&
|
|
|
|
(opcode == J2_endloop0 ||
|
|
|
|
opcode == J2_endloop1 ||
|
|
|
|
opcode == J2_endloop01)) {
|
|
|
|
is_predicated = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx_log_reg_write(ctx, rnum, is_predicated);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mark_implicit_reg_writes(DisasContext *ctx)
|
|
|
|
{
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
|
|
|
|
mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
|
|
|
|
mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum)
|
|
|
|
{
|
|
|
|
if (GET_ATTRIB(ctx->insn->opcode, attrib)) {
|
|
|
|
ctx_log_pred_write(ctx, pnum);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mark_implicit_pred_writes(DisasContext *ctx)
|
|
|
|
{
|
|
|
|
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0);
|
|
|
|
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1);
|
|
|
|
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2);
|
|
|
|
mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void analyze_packet(DisasContext *ctx)
|
|
|
|
{
|
|
|
|
Packet *pkt = ctx->pkt;
|
2023-03-07 05:58:20 +03:00
|
|
|
ctx->need_pkt_has_store_s1 = false;
|
2023-03-07 05:58:19 +03:00
|
|
|
for (int i = 0; i < pkt->num_insns; i++) {
|
|
|
|
Insn *insn = &pkt->insn[i];
|
|
|
|
ctx->insn = insn;
|
|
|
|
if (opcode_analyze[insn->opcode]) {
|
|
|
|
opcode_analyze[insn->opcode](ctx);
|
|
|
|
}
|
|
|
|
mark_implicit_reg_writes(ctx);
|
|
|
|
mark_implicit_pred_writes(ctx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void gen_start_packet(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
Packet *pkt = ctx->pkt;
|
2021-02-08 08:46:19 +03:00
|
|
|
target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Clear out the disassembly context */
|
2022-11-08 19:29:01 +03:00
|
|
|
ctx->next_PC = next_PC;
|
2021-02-08 08:46:19 +03:00
|
|
|
ctx->reg_log_idx = 0;
|
|
|
|
bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
|
2023-03-07 05:58:19 +03:00
|
|
|
bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
|
2021-02-08 08:46:19 +03:00
|
|
|
ctx->preg_log_idx = 0;
|
2021-04-09 04:07:34 +03:00
|
|
|
bitmap_zero(ctx->pregs_written, NUM_PREGS);
|
2021-09-30 22:29:00 +03:00
|
|
|
ctx->future_vregs_idx = 0;
|
|
|
|
ctx->tmp_vregs_idx = 0;
|
|
|
|
ctx->vreg_log_idx = 0;
|
|
|
|
bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
|
|
|
|
bitmap_zero(ctx->vregs_updated, NUM_VREGS);
|
|
|
|
bitmap_zero(ctx->vregs_select, NUM_VREGS);
|
2023-03-07 05:58:21 +03:00
|
|
|
bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
|
|
|
|
bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
|
2021-09-30 22:29:00 +03:00
|
|
|
ctx->qreg_log_idx = 0;
|
2021-02-08 08:46:19 +03:00
|
|
|
for (i = 0; i < STORES_MAX; i++) {
|
|
|
|
ctx->store_width[i] = 0;
|
|
|
|
}
|
2021-04-09 04:07:35 +03:00
|
|
|
ctx->s1_store_processed = false;
|
2021-09-30 22:29:00 +03:00
|
|
|
ctx->pre_commit = true;
|
2021-02-08 08:46:19 +03:00
|
|
|
|
2023-03-07 05:58:19 +03:00
|
|
|
analyze_packet(ctx);
|
|
|
|
|
2023-03-07 05:58:20 +03:00
|
|
|
if (ctx->need_pkt_has_store_s1) {
|
|
|
|
tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
|
|
|
|
}
|
|
|
|
|
2023-03-07 05:58:19 +03:00
|
|
|
/*
|
|
|
|
* pregs_written is used both in the analyze phase as well as the code
|
|
|
|
* gen phase, so clear it again.
|
|
|
|
*/
|
|
|
|
bitmap_zero(ctx->pregs_written, NUM_PREGS);
|
|
|
|
|
2021-04-09 04:07:44 +03:00
|
|
|
if (HEX_DEBUG) {
|
|
|
|
/* Handy place to set a breakpoint before the packet executes */
|
|
|
|
gen_helper_debug_start_packet(cpu_env);
|
|
|
|
tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
/* Initialize the runtime state for packet semantics */
|
|
|
|
if (need_slot_cancelled(pkt)) {
|
|
|
|
tcg_gen_movi_tl(hex_slot_cancelled, 0);
|
|
|
|
}
|
|
|
|
if (pkt->pkt_has_cof) {
|
2022-11-08 19:28:59 +03:00
|
|
|
if (pkt->pkt_has_multi_cof) {
|
|
|
|
tcg_gen_movi_tl(hex_branch_taken, 0);
|
|
|
|
}
|
2022-11-08 19:29:01 +03:00
|
|
|
if (need_next_PC(ctx)) {
|
|
|
|
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
if (need_pred_written(pkt)) {
|
|
|
|
tcg_gen_movi_tl(hex_pred_written, 0);
|
|
|
|
}
|
2021-09-30 22:29:00 +03:00
|
|
|
|
2023-03-07 05:58:19 +03:00
|
|
|
/* Preload the predicated registers into hex_new_value[i] */
|
|
|
|
if (!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
|
|
|
|
int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
|
|
|
|
while (i < TOTAL_PER_THREAD_REGS) {
|
|
|
|
tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]);
|
|
|
|
i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
|
|
|
|
i + 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-03-07 05:58:21 +03:00
|
|
|
/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
|
|
|
|
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
|
|
|
|
int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
|
|
|
|
while (i < NUM_VREGS) {
|
|
|
|
const intptr_t VdV_off =
|
|
|
|
ctx_future_vreg_off(ctx, i, 1, true);
|
|
|
|
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
|
|
|
|
tcg_gen_gvec_mov(MO_64, VdV_off,
|
|
|
|
src_off,
|
|
|
|
sizeof(MMVector),
|
|
|
|
sizeof(MMVector));
|
|
|
|
i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
|
|
|
|
int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
|
|
|
|
while (i < NUM_VREGS) {
|
|
|
|
const intptr_t VdV_off =
|
|
|
|
ctx_tmp_vreg_off(ctx, i, 1, true);
|
|
|
|
intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]);
|
|
|
|
tcg_gen_gvec_mov(MO_64, VdV_off,
|
|
|
|
src_off,
|
|
|
|
sizeof(MMVector),
|
|
|
|
sizeof(MMVector));
|
|
|
|
i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1);
|
|
|
|
}
|
|
|
|
}
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
bool is_gather_store_insn(DisasContext *ctx)
|
2021-09-30 22:29:00 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
Packet *pkt = ctx->pkt;
|
|
|
|
Insn *insn = ctx->insn;
|
2021-09-30 22:29:00 +03:00
|
|
|
if (GET_ATTRIB(insn->opcode, A_CVI_NEW) &&
|
|
|
|
insn->new_value_producer_slot == 1) {
|
|
|
|
/* Look for gather instruction */
|
|
|
|
for (int i = 0; i < pkt->num_insns; i++) {
|
|
|
|
Insn *in = &pkt->insn[i];
|
|
|
|
if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void mark_store_width(DisasContext *ctx)
|
2022-09-20 11:07:45 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
uint16_t opcode = ctx->insn->opcode;
|
|
|
|
uint32_t slot = ctx->insn->slot;
|
2022-09-20 11:07:45 +03:00
|
|
|
uint8_t width = 0;
|
|
|
|
|
|
|
|
if (GET_ATTRIB(opcode, A_SCALAR_STORE)) {
|
|
|
|
if (GET_ATTRIB(opcode, A_MEMSIZE_1B)) {
|
|
|
|
width |= 1;
|
|
|
|
}
|
|
|
|
if (GET_ATTRIB(opcode, A_MEMSIZE_2B)) {
|
|
|
|
width |= 2;
|
|
|
|
}
|
|
|
|
if (GET_ATTRIB(opcode, A_MEMSIZE_4B)) {
|
|
|
|
width |= 4;
|
|
|
|
}
|
|
|
|
if (GET_ATTRIB(opcode, A_MEMSIZE_8B)) {
|
|
|
|
width |= 8;
|
|
|
|
}
|
|
|
|
tcg_debug_assert(is_power_of_2(width));
|
|
|
|
ctx->store_width[slot] = width;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void gen_insn(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
if (ctx->insn->generate) {
|
|
|
|
ctx->insn->generate(ctx);
|
|
|
|
mark_store_width(ctx);
|
2021-02-08 08:46:19 +03:00
|
|
|
} else {
|
2021-04-09 04:07:33 +03:00
|
|
|
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Helpers for generating the packet commit
|
|
|
|
*/
|
|
|
|
static void gen_reg_writes(DisasContext *ctx)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ctx->reg_log_idx; i++) {
|
|
|
|
int reg_num = ctx->reg_log[i];
|
|
|
|
|
|
|
|
tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]);
|
2022-11-10 20:49:35 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* ctx->is_tight_loop is set when SA0 points to the beginning of the TB.
|
|
|
|
* If we write to SA0, we have to turn off tight loop handling.
|
|
|
|
*/
|
|
|
|
if (reg_num == HEX_REG_SA0) {
|
|
|
|
ctx->is_tight_loop = false;
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void gen_pred_writes(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Early exit if the log is empty */
|
|
|
|
if (!ctx->preg_log_idx) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only endloop instructions will conditionally
|
|
|
|
* write a predicate. If there are no endloop
|
|
|
|
* instructions, we can use the non-conditional
|
|
|
|
* write of the predicates.
|
|
|
|
*/
|
2022-11-08 19:28:56 +03:00
|
|
|
if (ctx->pkt->pkt_has_endloop) {
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv zero = tcg_constant_tl(0);
|
2021-02-08 08:46:19 +03:00
|
|
|
TCGv pred_written = tcg_temp_new();
|
|
|
|
for (i = 0; i < ctx->preg_log_idx; i++) {
|
|
|
|
int pred_num = ctx->preg_log[i];
|
|
|
|
|
|
|
|
tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num);
|
|
|
|
tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num],
|
|
|
|
pred_written, zero,
|
|
|
|
hex_new_pred_value[pred_num],
|
|
|
|
hex_pred[pred_num]);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < ctx->preg_log_idx; i++) {
|
|
|
|
int pred_num = ctx->preg_log[i];
|
|
|
|
tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
|
2021-04-09 04:07:44 +03:00
|
|
|
if (HEX_DEBUG) {
|
|
|
|
/* Do this so HELPER(debug_commit_end) will know */
|
|
|
|
tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
|
|
|
|
1 << pred_num);
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-15 07:53:04 +03:00
|
|
|
static void gen_check_store_width(DisasContext *ctx, int slot_num)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2021-04-09 04:07:44 +03:00
|
|
|
if (HEX_DEBUG) {
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv slot = tcg_constant_tl(slot_num);
|
|
|
|
TCGv check = tcg_constant_tl(ctx->store_width[slot_num]);
|
2021-04-09 04:07:44 +03:00
|
|
|
gen_helper_debug_check_store_width(cpu_env, slot, check);
|
|
|
|
}
|
2021-03-15 07:53:04 +03:00
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
static bool slot_is_predicated(Packet *pkt, int slot_num)
|
|
|
|
{
|
|
|
|
for (int i = 0; i < pkt->num_insns; i++) {
|
|
|
|
if (pkt->insn[i].slot == slot_num) {
|
|
|
|
return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* If we get to here, we didn't find an instruction in the requested slot */
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
void process_store(DisasContext *ctx, int slot_num)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
bool is_predicated = slot_is_predicated(ctx->pkt, slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
TCGLabel *label_end = NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We may have already processed this store
|
|
|
|
* See CHECK_NOSHUF in macros.h
|
|
|
|
*/
|
|
|
|
if (slot_num == 1 && ctx->s1_store_processed) {
|
|
|
|
return;
|
|
|
|
}
|
2021-04-09 04:07:35 +03:00
|
|
|
ctx->s1_store_processed = true;
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
if (is_predicated) {
|
|
|
|
TCGv cancelled = tcg_temp_new();
|
|
|
|
label_end = gen_new_label();
|
|
|
|
|
|
|
|
/* Don't do anything if the slot was cancelled */
|
|
|
|
tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
|
|
|
|
tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
|
|
|
|
}
|
|
|
|
{
|
2023-01-30 03:41:33 +03:00
|
|
|
TCGv address = tcg_temp_new();
|
2021-02-08 08:46:19 +03:00
|
|
|
tcg_gen_mov_tl(address, hex_store_addr[slot_num]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we know the width from the DisasContext, we can
|
|
|
|
* generate much cleaner code.
|
|
|
|
* Unfortunately, not all instructions execute the fSTORE
|
|
|
|
* macro during code generation. Anything that uses the
|
|
|
|
* generic helper will have this problem. Instructions
|
|
|
|
* that use fWRAP to generate proper TCG code will be OK.
|
|
|
|
*/
|
|
|
|
switch (ctx->store_width[slot_num]) {
|
|
|
|
case 1:
|
2021-03-15 07:53:04 +03:00
|
|
|
gen_check_store_width(ctx, slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
tcg_gen_qemu_st8(hex_store_val32[slot_num],
|
|
|
|
hex_store_addr[slot_num],
|
|
|
|
ctx->mem_idx);
|
|
|
|
break;
|
|
|
|
case 2:
|
2021-03-15 07:53:04 +03:00
|
|
|
gen_check_store_width(ctx, slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
tcg_gen_qemu_st16(hex_store_val32[slot_num],
|
|
|
|
hex_store_addr[slot_num],
|
|
|
|
ctx->mem_idx);
|
|
|
|
break;
|
|
|
|
case 4:
|
2021-03-15 07:53:04 +03:00
|
|
|
gen_check_store_width(ctx, slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
tcg_gen_qemu_st32(hex_store_val32[slot_num],
|
|
|
|
hex_store_addr[slot_num],
|
|
|
|
ctx->mem_idx);
|
|
|
|
break;
|
|
|
|
case 8:
|
2021-03-15 07:53:04 +03:00
|
|
|
gen_check_store_width(ctx, slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
tcg_gen_qemu_st64(hex_store_val64[slot_num],
|
|
|
|
hex_store_addr[slot_num],
|
|
|
|
ctx->mem_idx);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* If we get to here, we don't know the width at
|
|
|
|
* TCG generation time, we'll use a helper to
|
|
|
|
* avoid branching based on the width at runtime.
|
|
|
|
*/
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv slot = tcg_constant_tl(slot_num);
|
2021-02-08 08:46:19 +03:00
|
|
|
gen_helper_commit_store(cpu_env, slot);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (is_predicated) {
|
|
|
|
gen_set_label(label_end);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void process_store_log(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* When a packet has two stores, the hardware processes
|
2021-09-22 18:30:46 +03:00
|
|
|
* slot 1 and then slot 0. This will be important when
|
2021-02-08 08:46:19 +03:00
|
|
|
* the memory accesses overlap.
|
|
|
|
*/
|
2022-11-08 19:28:56 +03:00
|
|
|
Packet *pkt = ctx->pkt;
|
2022-09-20 11:07:46 +03:00
|
|
|
if (pkt->pkt_has_store_s1) {
|
|
|
|
g_assert(!pkt->pkt_has_dczeroa);
|
2022-11-08 19:28:56 +03:00
|
|
|
process_store(ctx, 1);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
2022-09-20 11:07:46 +03:00
|
|
|
if (pkt->pkt_has_store_s0) {
|
|
|
|
g_assert(!pkt->pkt_has_dczeroa);
|
2022-11-08 19:28:56 +03:00
|
|
|
process_store(ctx, 0);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Zero out a 32-bit cache line */
|
2022-11-08 19:28:56 +03:00
|
|
|
static void process_dczeroa(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
if (ctx->pkt->pkt_has_dczeroa) {
|
2021-02-08 08:46:19 +03:00
|
|
|
/* Store 32 bytes of zero starting at (addr & ~0x1f) */
|
|
|
|
TCGv addr = tcg_temp_new();
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv_i64 zero = tcg_constant_i64(0);
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
|
|
|
|
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
|
|
tcg_gen_addi_tl(addr, addr, 8);
|
|
|
|
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
|
|
tcg_gen_addi_tl(addr, addr, 8);
|
|
|
|
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
|
|
tcg_gen_addi_tl(addr, addr, 8);
|
|
|
|
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-30 22:29:00 +03:00
|
|
|
static bool pkt_has_hvx_store(Packet *pkt)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < pkt->num_insns; i++) {
|
|
|
|
int opcode = pkt->insn[i].opcode;
|
|
|
|
if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_STORE)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void gen_commit_hvx(DisasContext *ctx)
|
2021-09-30 22:29:00 +03:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* for (i = 0; i < ctx->vreg_log_idx; i++) {
|
|
|
|
* int rnum = ctx->vreg_log[i];
|
2023-03-07 05:58:28 +03:00
|
|
|
* env->VRegs[rnum] = env->future_VRegs[rnum];
|
2021-09-30 22:29:00 +03:00
|
|
|
* }
|
|
|
|
*/
|
|
|
|
for (i = 0; i < ctx->vreg_log_idx; i++) {
|
|
|
|
int rnum = ctx->vreg_log[i];
|
|
|
|
intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]);
|
|
|
|
intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false);
|
|
|
|
size_t size = sizeof(MMVector);
|
|
|
|
|
2023-03-07 05:58:28 +03:00
|
|
|
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* for (i = 0; i < ctx->qreg_log_idx; i++) {
|
|
|
|
* int rnum = ctx->qreg_log[i];
|
2023-03-07 05:58:28 +03:00
|
|
|
* env->QRegs[rnum] = env->future_QRegs[rnum];
|
2021-09-30 22:29:00 +03:00
|
|
|
* }
|
|
|
|
*/
|
|
|
|
for (i = 0; i < ctx->qreg_log_idx; i++) {
|
|
|
|
int rnum = ctx->qreg_log[i];
|
|
|
|
intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]);
|
|
|
|
intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]);
|
|
|
|
size_t size = sizeof(MMQReg);
|
|
|
|
|
2023-03-07 05:58:28 +03:00
|
|
|
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
if (pkt_has_hvx_store(ctx->pkt)) {
|
2021-09-30 22:29:00 +03:00
|
|
|
gen_helper_commit_hvx_stores(cpu_env);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void update_exec_counters(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-11-08 19:28:56 +03:00
|
|
|
Packet *pkt = ctx->pkt;
|
2021-02-08 08:46:19 +03:00
|
|
|
int num_insns = pkt->num_insns;
|
|
|
|
int num_real_insns = 0;
|
2021-09-30 22:29:00 +03:00
|
|
|
int num_hvx_insns = 0;
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
for (int i = 0; i < num_insns; i++) {
|
|
|
|
if (!pkt->insn[i].is_endloop &&
|
|
|
|
!pkt->insn[i].part1 &&
|
|
|
|
!GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) {
|
|
|
|
num_real_insns++;
|
|
|
|
}
|
2021-09-30 22:29:00 +03:00
|
|
|
if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) {
|
|
|
|
num_hvx_insns++;
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
ctx->num_packets++;
|
|
|
|
ctx->num_insns += num_real_insns;
|
2021-09-30 22:29:00 +03:00
|
|
|
ctx->num_hvx_insns += num_hvx_insns;
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
static void gen_commit_packet(DisasContext *ctx)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2021-09-22 18:30:46 +03:00
|
|
|
/*
|
|
|
|
* If there is more than one store in a packet, make sure they are all OK
|
|
|
|
* before proceeding with the rest of the packet commit.
|
|
|
|
*
|
|
|
|
* dczeroa has to be the only store operation in the packet, so we go
|
|
|
|
* ahead and process that first.
|
|
|
|
*
|
2021-09-30 22:29:00 +03:00
|
|
|
* When there is an HVX store, there can also be a scalar store in either
|
|
|
|
* slot 0 or slot1, so we create a mask for the helper to indicate what
|
|
|
|
* work to do.
|
|
|
|
*
|
2021-09-22 18:30:46 +03:00
|
|
|
* When there are two scalar stores, we probe the one in slot 0.
|
|
|
|
*
|
|
|
|
* Note that we don't call the probe helper for packets with only one
|
|
|
|
* store. Therefore, we call process_store_log before anything else
|
|
|
|
* involved in committing the packet.
|
|
|
|
*/
|
2022-11-08 19:28:56 +03:00
|
|
|
Packet *pkt = ctx->pkt;
|
2021-09-22 18:30:46 +03:00
|
|
|
bool has_store_s0 = pkt->pkt_has_store_s0;
|
|
|
|
bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
|
2021-09-30 22:29:00 +03:00
|
|
|
bool has_hvx_store = pkt_has_hvx_store(pkt);
|
2021-09-22 18:30:46 +03:00
|
|
|
if (pkt->pkt_has_dczeroa) {
|
|
|
|
/*
|
|
|
|
* The dczeroa will be the store in slot 0, check that we don't have
|
2021-09-30 22:29:00 +03:00
|
|
|
* a store in slot 1 or an HVX store.
|
2021-09-22 18:30:46 +03:00
|
|
|
*/
|
2022-09-20 11:07:46 +03:00
|
|
|
g_assert(!has_store_s1 && !has_hvx_store);
|
2022-11-08 19:28:56 +03:00
|
|
|
process_dczeroa(ctx);
|
2021-09-30 22:29:00 +03:00
|
|
|
} else if (has_hvx_store) {
|
|
|
|
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
|
|
|
|
|
|
|
|
if (!has_store_s0 && !has_store_s1) {
|
|
|
|
gen_helper_probe_hvx_stores(cpu_env, mem_idx);
|
|
|
|
} else {
|
|
|
|
int mask = 0;
|
|
|
|
TCGv mask_tcgv;
|
|
|
|
|
|
|
|
if (has_store_s0) {
|
Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
|
|
|
mask =
|
|
|
|
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 1);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
if (has_store_s1) {
|
Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
|
|
|
mask =
|
|
|
|
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
if (has_hvx_store) {
|
Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
|
|
|
mask =
|
|
|
|
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
|
|
|
|
HAS_HVX_STORES, 1);
|
|
|
|
}
|
|
|
|
if (has_store_s0 && slot_is_predicated(pkt, 0)) {
|
|
|
|
mask =
|
|
|
|
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
|
|
|
|
S0_IS_PRED, 1);
|
|
|
|
}
|
|
|
|
if (has_store_s1 && slot_is_predicated(pkt, 1)) {
|
|
|
|
mask =
|
|
|
|
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
|
|
|
|
S1_IS_PRED, 1);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
mask_tcgv = tcg_constant_tl(mask);
|
|
|
|
gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx);
|
|
|
|
}
|
2021-09-22 18:30:46 +03:00
|
|
|
} else if (has_store_s0 && has_store_s1) {
|
|
|
|
/*
|
|
|
|
* process_store_log will execute the slot 1 store first,
|
|
|
|
* so we only have to probe the store in slot 0
|
|
|
|
*/
|
Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-07 05:58:27 +03:00
|
|
|
int args = 0;
|
|
|
|
args =
|
|
|
|
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx);
|
|
|
|
if (slot_is_predicated(pkt, 0)) {
|
|
|
|
args =
|
|
|
|
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
|
|
|
|
}
|
|
|
|
TCGv args_tcgv = tcg_constant_tl(args);
|
|
|
|
gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv);
|
2021-09-22 18:30:46 +03:00
|
|
|
}
|
|
|
|
|
2022-11-08 19:28:56 +03:00
|
|
|
process_store_log(ctx);
|
2021-09-22 18:30:46 +03:00
|
|
|
|
2021-02-08 08:46:19 +03:00
|
|
|
gen_reg_writes(ctx);
|
2022-11-08 19:28:56 +03:00
|
|
|
gen_pred_writes(ctx);
|
2021-09-30 22:29:00 +03:00
|
|
|
if (pkt->pkt_has_hvx) {
|
2022-11-08 19:28:56 +03:00
|
|
|
gen_commit_hvx(ctx);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
2022-11-08 19:28:56 +03:00
|
|
|
update_exec_counters(ctx);
|
2021-04-09 04:07:44 +03:00
|
|
|
if (HEX_DEBUG) {
|
2021-02-08 08:46:19 +03:00
|
|
|
TCGv has_st0 =
|
2021-10-03 03:47:50 +03:00
|
|
|
tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
|
2021-02-08 08:46:19 +03:00
|
|
|
TCGv has_st1 =
|
2021-10-03 03:47:50 +03:00
|
|
|
tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
/* Handy place to set a breakpoint at the end of execution */
|
|
|
|
gen_helper_debug_commit_end(cpu_env, has_st0, has_st1);
|
|
|
|
}
|
|
|
|
|
2021-09-30 22:29:00 +03:00
|
|
|
if (pkt->vhist_insn != NULL) {
|
|
|
|
ctx->pre_commit = false;
|
2022-11-08 19:28:56 +03:00
|
|
|
ctx->insn = pkt->vhist_insn;
|
|
|
|
pkt->vhist_insn->generate(ctx);
|
2021-09-30 22:29:00 +03:00
|
|
|
}
|
|
|
|
|
2021-02-08 08:46:19 +03:00
|
|
|
if (pkt->pkt_has_cof) {
|
2021-04-09 04:07:33 +03:00
|
|
|
gen_end_tb(ctx);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
|
|
|
|
{
|
|
|
|
uint32_t words[PACKET_WORDS_MAX];
|
|
|
|
int nwords;
|
|
|
|
Packet pkt;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
nwords = read_packet_words(env, ctx, words);
|
|
|
|
if (!nwords) {
|
2021-04-09 04:07:33 +03:00
|
|
|
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
|
2021-02-08 08:46:19 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (decode_packet(nwords, words, &pkt, false) > 0) {
|
2022-11-08 19:29:00 +03:00
|
|
|
pkt.pc = ctx->base.pc_next;
|
2021-02-08 08:46:19 +03:00
|
|
|
HEX_DEBUG_PRINT_PKT(&pkt);
|
2022-11-08 19:28:56 +03:00
|
|
|
ctx->pkt = &pkt;
|
|
|
|
gen_start_packet(ctx);
|
2021-02-08 08:46:19 +03:00
|
|
|
for (i = 0; i < pkt.num_insns; i++) {
|
2022-11-08 19:28:56 +03:00
|
|
|
ctx->insn = &pkt.insn[i];
|
|
|
|
gen_insn(ctx);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
2022-11-08 19:28:56 +03:00
|
|
|
gen_commit_packet(ctx);
|
2021-02-08 08:46:19 +03:00
|
|
|
ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
|
|
|
|
} else {
|
2021-04-09 04:07:33 +03:00
|
|
|
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
|
|
|
|
CPUState *cs)
|
|
|
|
{
|
|
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
2022-11-10 20:49:35 +03:00
|
|
|
uint32_t hex_flags = dcbase->tb->flags;
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
ctx->mem_idx = MMU_USER_IDX;
|
|
|
|
ctx->num_packets = 0;
|
|
|
|
ctx->num_insns = 0;
|
2021-09-30 22:29:00 +03:00
|
|
|
ctx->num_hvx_insns = 0;
|
2022-11-08 19:29:05 +03:00
|
|
|
ctx->branch_cond = TCG_COND_NEVER;
|
2022-11-10 20:49:35 +03:00
|
|
|
ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
|
|
|
{
|
|
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
|
|
|
|
tcg_gen_insn_start(ctx->base.pc_next);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)
|
|
|
|
{
|
|
|
|
target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
|
|
|
|
bool found_end = false;
|
|
|
|
int nwords;
|
|
|
|
|
|
|
|
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
|
|
|
|
uint32_t word = cpu_ldl_code(env,
|
|
|
|
ctx->base.pc_next + nwords * sizeof(uint32_t));
|
|
|
|
found_end = is_packet_end(word);
|
|
|
|
}
|
|
|
|
uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t);
|
|
|
|
return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
|
|
|
|
{
|
|
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
CPUHexagonState *env = cpu->env_ptr;
|
|
|
|
|
|
|
|
decode_and_translate_packet(env, ctx);
|
|
|
|
|
|
|
|
if (ctx->base.is_jmp == DISAS_NEXT) {
|
|
|
|
target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
|
|
|
|
target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong);
|
|
|
|
|
|
|
|
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE ||
|
|
|
|
(ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max &&
|
|
|
|
pkt_crosses_page(env, ctx))) {
|
|
|
|
ctx->base.is_jmp = DISAS_TOO_MANY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The CPU log is used to compare against LLDB single stepping,
|
|
|
|
* so end the TLB after every packet.
|
|
|
|
*/
|
2021-04-09 04:07:32 +03:00
|
|
|
HexagonCPU *hex_cpu = env_archcpu(env);
|
2021-02-08 08:46:19 +03:00
|
|
|
if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
|
|
|
|
ctx->base.is_jmp = DISAS_TOO_MANY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|
|
|
{
|
|
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
|
|
|
|
switch (ctx->base.is_jmp) {
|
|
|
|
case DISAS_TOO_MANY:
|
|
|
|
gen_exec_counters(ctx);
|
|
|
|
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
|
2021-07-19 10:02:03 +03:00
|
|
|
tcg_gen_exit_tb(NULL, 0);
|
2021-02-08 08:46:19 +03:00
|
|
|
break;
|
|
|
|
case DISAS_NORETURN:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-04-17 21:29:52 +03:00
|
|
|
static void hexagon_tr_disas_log(const DisasContextBase *dcbase,
|
|
|
|
CPUState *cpu, FILE *logfile)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
2022-04-17 21:29:52 +03:00
|
|
|
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
|
|
|
|
target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static const TranslatorOps hexagon_tr_ops = {
|
|
|
|
.init_disas_context = hexagon_tr_init_disas_context,
|
|
|
|
.tb_start = hexagon_tr_tb_start,
|
|
|
|
.insn_start = hexagon_tr_insn_start,
|
|
|
|
.translate_insn = hexagon_tr_translate_packet,
|
|
|
|
.tb_stop = hexagon_tr_tb_stop,
|
|
|
|
.disas_log = hexagon_tr_disas_log,
|
|
|
|
};
|
|
|
|
|
2023-01-29 04:19:22 +03:00
|
|
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
|
2022-08-11 23:48:03 +03:00
|
|
|
target_ulong pc, void *host_pc)
|
2021-02-08 08:46:19 +03:00
|
|
|
{
|
|
|
|
DisasContext ctx;
|
|
|
|
|
2022-08-11 23:48:03 +03:00
|
|
|
translator_loop(cs, tb, max_insns, pc, host_pc,
|
|
|
|
&hexagon_tr_ops, &ctx.base);
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
#define NAME_LEN 64
|
|
|
|
static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
|
|
|
|
static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
|
|
|
|
static char new_pred_value_names[NUM_PREGS][NAME_LEN];
|
|
|
|
static char store_addr_names[STORES_MAX][NAME_LEN];
|
|
|
|
static char store_width_names[STORES_MAX][NAME_LEN];
|
|
|
|
static char store_val32_names[STORES_MAX][NAME_LEN];
|
|
|
|
static char store_val64_names[STORES_MAX][NAME_LEN];
|
2021-09-30 22:29:00 +03:00
|
|
|
static char vstore_addr_names[VSTORES_MAX][NAME_LEN];
|
|
|
|
static char vstore_size_names[VSTORES_MAX][NAME_LEN];
|
|
|
|
static char vstore_pending_names[VSTORES_MAX][NAME_LEN];
|
2021-02-08 08:46:19 +03:00
|
|
|
|
|
|
|
void hexagon_translate_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
opcode_init();
|
|
|
|
|
|
|
|
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
|
|
|
|
hex_gpr[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, gpr[i]),
|
|
|
|
hexagon_regnames[i]);
|
|
|
|
|
|
|
|
snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]);
|
|
|
|
hex_new_value[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, new_value[i]),
|
|
|
|
new_value_names[i]);
|
|
|
|
|
2021-04-09 04:07:44 +03:00
|
|
|
if (HEX_DEBUG) {
|
|
|
|
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
|
|
|
|
hexagon_regnames[i]);
|
|
|
|
hex_reg_written[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, reg_written[i]),
|
|
|
|
reg_written_names[i]);
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|
|
|
|
for (i = 0; i < NUM_PREGS; i++) {
|
|
|
|
hex_pred[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, pred[i]),
|
|
|
|
hexagon_prednames[i]);
|
|
|
|
|
|
|
|
snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s",
|
|
|
|
hexagon_prednames[i]);
|
|
|
|
hex_new_pred_value[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, new_pred_value[i]),
|
|
|
|
new_pred_value_names[i]);
|
|
|
|
}
|
|
|
|
hex_pred_written = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, pred_written), "pred_written");
|
|
|
|
hex_this_PC = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, this_PC), "this_PC");
|
|
|
|
hex_slot_cancelled = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
|
|
|
|
hex_branch_taken = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, branch_taken), "branch_taken");
|
|
|
|
hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1");
|
|
|
|
hex_dczero_addr = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, dczero_addr), "dczero_addr");
|
|
|
|
hex_llsc_addr = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
|
|
|
|
hex_llsc_val = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, llsc_val), "llsc_val");
|
|
|
|
hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
|
|
|
|
for (i = 0; i < STORES_MAX; i++) {
|
|
|
|
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
|
|
|
|
hex_store_addr[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, mem_log_stores[i].va),
|
|
|
|
store_addr_names[i]);
|
|
|
|
|
|
|
|
snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
|
|
|
|
hex_store_width[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, mem_log_stores[i].width),
|
|
|
|
store_width_names[i]);
|
|
|
|
|
|
|
|
snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
|
|
|
|
hex_store_val32[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, mem_log_stores[i].data32),
|
|
|
|
store_val32_names[i]);
|
|
|
|
|
|
|
|
snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
|
|
|
|
hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, mem_log_stores[i].data64),
|
|
|
|
store_val64_names[i]);
|
|
|
|
}
|
2021-09-30 22:29:00 +03:00
|
|
|
for (int i = 0; i < VSTORES_MAX; i++) {
|
|
|
|
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
|
|
|
|
hex_vstore_addr[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, vstore[i].va),
|
|
|
|
vstore_addr_names[i]);
|
|
|
|
|
|
|
|
snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i);
|
|
|
|
hex_vstore_size[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, vstore[i].size),
|
|
|
|
vstore_size_names[i]);
|
|
|
|
|
|
|
|
snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i);
|
|
|
|
hex_vstore_pending[i] = tcg_global_mem_new(cpu_env,
|
|
|
|
offsetof(CPUHexagonState, vstore_pending[i]),
|
|
|
|
vstore_pending_names[i]);
|
|
|
|
}
|
2021-02-08 08:46:19 +03:00
|
|
|
}
|