2022-06-06 15:42:53 +03:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch translation routines.
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef TARGET_LOONGARCH_TRANSLATE_H
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#define TARGET_LOONGARCH_TRANSLATE_H
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#include "exec/translator.h"
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2023-08-22 10:19:51 +03:00
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#define TRANS(NAME, AVAIL, FUNC, ...) \
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
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2023-08-22 10:19:51 +03:00
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{ return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
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#define avail_ALL(C) true
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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/*
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* If an operation is being performed on less than TARGET_LONG_BITS,
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* it may require the inputs to be sign- or zero-extended; which will
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* depend on the exact operation being performed.
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*/
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typedef enum {
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EXT_NONE,
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EXT_SIGN,
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EXT_ZERO,
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} DisasExtend;
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2022-06-06 15:42:53 +03:00
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong page_start;
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uint32_t opcode;
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2022-11-07 05:45:25 +03:00
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uint16_t mem_idx;
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uint16_t plv;
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2023-05-04 15:27:30 +03:00
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int vl; /* Vector length */
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target/loongarch: Add fixed point arithmetic instruction translation
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06 15:42:54 +03:00
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TCGv zero;
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2023-08-22 10:13:50 +03:00
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bool la64; /* LoongArch64 mode */
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bool va32; /* 32-bit virtual address */
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2022-06-06 15:42:53 +03:00
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} DisasContext;
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void generate_exception(DisasContext *ctx, int excp);
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extern TCGv cpu_gpr[32], cpu_pc;
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extern TCGv_i32 cpu_fscr0;
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extern TCGv_i64 cpu_fpr[32];
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#endif
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