18 lines
683 B
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18 lines
683 B
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OpenRISC 1000 CPU architecture support
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QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
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the OpenRISC 1000 cpu architecture.
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The or1200 cpu also has support for the following instruction subsets:
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- ORBIS32 (OpenRISC Basic Instruction Set)
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- ORFPX32 (OpenRISC Floating-Point eXtension)
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In addition to the instruction subsets the QEMU TCG emulation also has support
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for most Class II (optional) instructions.
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For information on all OpenRISC instructions please refer to the latest
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architecture manual available on the OpenRISC website in the
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`OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
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