mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
e73f27003e
qemu/configs/devices/riscv32-softmmu/default.mak

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

16 lines
296 B
Makefile
Raw Normal View History

riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives %-softmmu.mak only keep boards and optional device definitions in Kconfig mode. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-29 14:16:27 +03:00
# Default configuration for riscv32-softmmu
RISC-V Build Infrastructure This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-02 15:32:59 +03:00
riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives %-softmmu.mak only keep boards and optional device definitions in Kconfig mode. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-29 14:16:27 +03:00
# Uncomment the following lines to disable these optional devices:
#
#CONFIG_PCI_DEVICES=n
riscv: Add semihosting support Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-09 01:42:52 +03:00
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards Add the new configs to default-configs/riscv*-sofmmu.mak. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-19-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-02 10:24:47 +03:00
riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives %-softmmu.mak only keep boards and optional device definitions in Kconfig mode. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-29 14:16:27 +03:00
# Boards:
#
hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards Add the new configs to default-configs/riscv*-sofmmu.mak. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-19-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-02 10:24:47 +03:00
CONFIG_SPIKE=y
CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 21:30:50 +03:00
CONFIG_OPENTITAN=y
Reference in New Issue Copy Permalink