2021-05-12 13:20:36 +03:00
|
|
|
/* Helpers */
|
|
|
|
#define LI(reg, val) \
|
|
|
|
mov.u reg, lo:val; \
|
|
|
|
movh DREG_TEMP_LI, up:val; \
|
|
|
|
or reg, reg, DREG_TEMP_LI; \
|
|
|
|
|
2023-02-02 15:04:32 +03:00
|
|
|
#define LIA(reg, val) \
|
|
|
|
LI(DREG_TEMP, val) \
|
|
|
|
mov.a reg, DREG_TEMP;
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
/* Address definitions */
|
|
|
|
#define TESTDEV_ADDR 0xf0000000
|
|
|
|
/* Register definitions */
|
|
|
|
#define DREG_RS1 %d0
|
2021-05-12 13:20:37 +03:00
|
|
|
#define DREG_RS2 %d1
|
2023-02-02 15:04:26 +03:00
|
|
|
#define DREG_RS3 %d2
|
|
|
|
#define DREG_CALC_RESULT %d3
|
|
|
|
#define DREG_CALC_PSW %d4
|
|
|
|
#define DREG_CORRECT_PSW %d5
|
2021-05-12 13:20:36 +03:00
|
|
|
#define DREG_TEMP_LI %d10
|
|
|
|
#define DREG_TEMP %d11
|
|
|
|
#define DREG_TEST_NUM %d14
|
|
|
|
#define DREG_CORRECT_RESULT %d15
|
2023-02-03 16:21:32 +03:00
|
|
|
#define DREG_CORRECT_RESULT_2 %d13
|
2021-05-12 13:20:36 +03:00
|
|
|
|
2023-02-02 15:04:32 +03:00
|
|
|
#define AREG_ADDR %a0
|
|
|
|
#define AREG_CORRECT_RESULT %a3
|
|
|
|
#define MEM_BASE_ADDR 0xd0000000
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
#define DREG_DEV_ADDR %a15
|
|
|
|
|
2021-05-12 13:20:39 +03:00
|
|
|
#define EREG_RS1 %e6
|
|
|
|
#define EREG_RS1_LO %d6
|
|
|
|
#define EREG_RS1_HI %d7
|
|
|
|
#define EREG_RS2 %e8
|
|
|
|
#define EREG_RS2_LO %d8
|
|
|
|
#define EREG_RS2_HI %d9
|
|
|
|
#define EREG_CALC_RESULT %e8
|
|
|
|
#define EREG_CALC_RESULT_HI %d9
|
|
|
|
#define EREG_CALC_RESULT_LO %d8
|
|
|
|
#define EREG_CORRECT_RESULT_LO %d0
|
|
|
|
#define EREG_CORRECT_RESULT_HI %d1
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
/* Test case wrappers */
|
|
|
|
#define TEST_CASE(num, testreg, correct, code...) \
|
|
|
|
test_ ## num: \
|
|
|
|
code; \
|
|
|
|
LI(DREG_CORRECT_RESULT, correct) \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
jne testreg, DREG_CORRECT_RESULT, fail \
|
|
|
|
|
2021-05-12 13:20:39 +03:00
|
|
|
#define TEST_CASE_E(num, correct_lo, correct_hi, code...) \
|
|
|
|
test_ ## num: \
|
|
|
|
code; \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
LI(EREG_CORRECT_RESULT_LO, correct_lo) \
|
|
|
|
jne EREG_CALC_RESULT_LO, EREG_CORRECT_RESULT_LO, fail; \
|
|
|
|
LI(EREG_CORRECT_RESULT_HI, correct_hi) \
|
|
|
|
jne EREG_CALC_RESULT_HI, EREG_CORRECT_RESULT_HI, fail;
|
|
|
|
|
2021-05-12 13:20:37 +03:00
|
|
|
#define TEST_CASE_PSW(num, testreg, correct, correct_psw, code...) \
|
|
|
|
test_ ## num: \
|
|
|
|
code; \
|
|
|
|
LI(DREG_CORRECT_RESULT, correct) \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
jne testreg, DREG_CORRECT_RESULT, fail; \
|
|
|
|
mfcr DREG_CALC_PSW, $psw; \
|
|
|
|
LI(DREG_CORRECT_PSW, correct_psw) \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
jne DREG_CALC_PSW, DREG_CORRECT_PSW, fail;
|
|
|
|
|
2023-02-02 15:04:32 +03:00
|
|
|
#define TEST_LD(insn, num, result, addr_result, ld_pattern) \
|
|
|
|
test_ ## num: \
|
|
|
|
LIA(AREG_ADDR, test_data) \
|
|
|
|
insn DREG_CALC_RESULT, ld_pattern; \
|
|
|
|
LI(DREG_CORRECT_RESULT, result) \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail; \
|
|
|
|
mov.d DREG_CALC_RESULT, AREG_ADDR; \
|
|
|
|
LI(DREG_CORRECT_RESULT, addr_result) \
|
|
|
|
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
|
|
|
|
|
2023-02-03 16:21:32 +03:00
|
|
|
#define TEST_LD_SRO(insn, num, result, addr_result, ld_pattern) \
|
|
|
|
test_ ## num: \
|
|
|
|
LIA(AREG_ADDR, test_data) \
|
|
|
|
insn %d15, ld_pattern; \
|
|
|
|
LI(DREG_CORRECT_RESULT_2, result) \
|
|
|
|
mov DREG_TEST_NUM, num; \
|
|
|
|
jne %d15, DREG_CORRECT_RESULT_2, fail; \
|
|
|
|
mov.d DREG_CALC_RESULT, AREG_ADDR; \
|
|
|
|
LI(DREG_CORRECT_RESULT, addr_result) \
|
|
|
|
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
|
|
|
|
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
/* Actual test case type
|
|
|
|
* e.g inst %dX, %dY -> TEST_D_D
|
|
|
|
* inst %dX, %dY, %dZ -> TEST_D_DD
|
|
|
|
* inst %eX, %dY, %dZ -> TEST_E_DD
|
|
|
|
*/
|
2023-02-02 15:04:32 +03:00
|
|
|
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
#define TEST_D_D(insn, num, result, rs1) \
|
|
|
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1; \
|
|
|
|
)
|
|
|
|
|
2021-05-12 13:20:42 +03:00
|
|
|
#define TEST_D_D_PSW(insn, num, result, psw, rs1) \
|
|
|
|
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CORRECT_RESULT, DREG_RS1; \
|
|
|
|
)
|
|
|
|
|
2023-02-02 15:04:30 +03:00
|
|
|
#define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \
|
|
|
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
LI(DREG_RS3, rs3); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
|
|
|
|
)
|
|
|
|
|
2021-05-12 13:20:37 +03:00
|
|
|
#define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
|
|
|
|
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
|
|
|
|
)
|
|
|
|
|
2021-05-12 13:20:43 +03:00
|
|
|
#define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \
|
|
|
|
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
LI(DREG_RS3, rs3); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
|
|
|
|
)
|
|
|
|
|
2023-02-02 15:04:28 +03:00
|
|
|
#define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \
|
|
|
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
|
|
|
|
)
|
|
|
|
|
2021-05-12 13:20:43 +03:00
|
|
|
#define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \
|
|
|
|
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
|
|
|
|
)
|
|
|
|
|
2023-02-02 15:04:26 +03:00
|
|
|
#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
|
|
|
|
TEST_CASE(num, DREG_CALC_RESULT, result, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
LI(DREG_RS2, rs1); \
|
|
|
|
rstv; \
|
|
|
|
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
|
|
|
|
)
|
|
|
|
|
2021-05-12 13:20:39 +03:00
|
|
|
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
|
|
|
|
TEST_CASE_E(num, res_lo, res_hi, \
|
|
|
|
LI(EREG_RS1_LO, rs1_lo); \
|
|
|
|
LI(EREG_RS1_HI, rs1_hi); \
|
|
|
|
LI(DREG_RS2, rs2); \
|
|
|
|
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
|
|
|
|
)
|
2021-05-12 13:20:37 +03:00
|
|
|
|
2023-02-02 15:04:24 +03:00
|
|
|
#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
|
|
|
|
TEST_CASE_E(num, res_lo, res_hi, \
|
|
|
|
LI(DREG_RS1, rs1); \
|
|
|
|
rstv; \
|
2023-02-28 22:06:40 +03:00
|
|
|
insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2; \
|
2023-02-02 15:04:24 +03:00
|
|
|
)
|
|
|
|
|
2023-02-02 15:04:32 +03:00
|
|
|
|
|
|
|
|
2021-05-12 13:20:36 +03:00
|
|
|
/* Pass/Fail handling part */
|
|
|
|
#define TEST_PASSFAIL \
|
|
|
|
j pass; \
|
|
|
|
fail: \
|
|
|
|
LI(DREG_TEMP, TESTDEV_ADDR) \
|
|
|
|
mov.a DREG_DEV_ADDR, DREG_TEMP; \
|
|
|
|
st.w [DREG_DEV_ADDR], DREG_TEST_NUM;\
|
|
|
|
debug; \
|
|
|
|
j fail; \
|
|
|
|
pass: \
|
|
|
|
LI(DREG_TEMP, TESTDEV_ADDR) \
|
|
|
|
mov.a DREG_DEV_ADDR, DREG_TEMP; \
|
|
|
|
mov DREG_TEST_NUM, 0; \
|
|
|
|
st.w [DREG_DEV_ADDR], DREG_TEST_NUM;\
|
|
|
|
debug; \
|
|
|
|
j pass;
|