22 lines
516 B
C
22 lines
516 B
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/*
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* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
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* for the initial upstreaming of this architecture, so don't bother and just
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* support the LP64* ABI for now.
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*/
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#if defined(__loongarch64)
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# define TCG_TARGET_REG_BITS 64
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#else
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# error unsupported LoongArch register size
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#endif
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#endif
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