2015-05-15 05:22:58 +03:00
|
|
|
/*
|
|
|
|
* Xilinx Zynq MPSoC emulation
|
|
|
|
*
|
|
|
|
* Copyright (C) 2015 Xilinx Inc
|
|
|
|
* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms of the GNU General Public License as published by the
|
|
|
|
* Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
|
|
* for more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef XLNX_ZYNQMP_H
|
2019-06-04 21:16:15 +03:00
|
|
|
#define XLNX_ZYNQMP_H
|
2015-05-15 05:22:58 +03:00
|
|
|
|
2015-05-15 05:23:01 +03:00
|
|
|
#include "hw/intc/arm_gic.h"
|
2015-05-15 05:23:12 +03:00
|
|
|
#include "hw/net/cadence_gem.h"
|
2015-05-15 05:23:21 +03:00
|
|
|
#include "hw/char/cadence_uart.h"
|
2020-11-18 22:48:44 +03:00
|
|
|
#include "hw/net/xlnx-zynqmp-can.h"
|
2015-09-08 19:38:45 +03:00
|
|
|
#include "hw/ide/ahci.h"
|
2015-10-08 16:21:03 +03:00
|
|
|
#include "hw/sd/sdhci.h"
|
2016-01-21 17:15:03 +03:00
|
|
|
#include "hw/ssi/xilinx_spips.h"
|
2016-06-14 17:59:15 +03:00
|
|
|
#include "hw/dma/xlnx_dpdma.h"
|
2018-05-18 19:48:07 +03:00
|
|
|
#include "hw/dma/xlnx-zdma.h"
|
2016-06-14 17:59:15 +03:00
|
|
|
#include "hw/display/xlnx_dp.h"
|
2018-01-22 22:43:52 +03:00
|
|
|
#include "hw/intc/xlnx-zynqmp-ipi.h"
|
2019-10-04 02:03:59 +03:00
|
|
|
#include "hw/rtc/xlnx-zynqmp-rtc.h"
|
2019-01-07 18:23:46 +03:00
|
|
|
#include "hw/cpu/cluster.h"
|
2019-08-12 08:23:31 +03:00
|
|
|
#include "target/arm/cpu.h"
|
2020-09-03 23:43:22 +03:00
|
|
|
#include "qom/object.h"
|
2020-11-18 22:48:44 +03:00
|
|
|
#include "net/can_emu.h"
|
2021-03-03 16:52:52 +03:00
|
|
|
#include "hw/dma/xlnx_csu_dma.h"
|
2021-09-17 08:23:58 +03:00
|
|
|
#include "hw/nvram/xlnx-bbram.h"
|
2021-09-17 08:23:59 +03:00
|
|
|
#include "hw/nvram/xlnx-zynqmp-efuse.h"
|
2022-02-03 18:17:42 +03:00
|
|
|
#include "hw/or-irq.h"
|
2022-03-16 19:46:45 +03:00
|
|
|
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
|
2022-03-16 19:46:43 +03:00
|
|
|
#include "hw/misc/xlnx-zynqmp-crf.h"
|
2022-04-01 01:20:17 +03:00
|
|
|
#include "hw/timer/cadence_ttc.h"
|
2022-09-20 11:15:17 +03:00
|
|
|
#include "hw/usb/hcd-dwc3.h"
|
2015-05-15 05:22:58 +03:00
|
|
|
|
hw: Replace anti-social QOM type names
Several QOM type names contain ',':
ARM,bitband-memory
etraxfs,pic
etraxfs,serial
etraxfs,timer
fsl,imx25
fsl,imx31
fsl,imx6
fsl,imx6ul
fsl,imx7
grlib,ahbpnp
grlib,apbpnp
grlib,apbuart
grlib,gptimer
grlib,irqmp
qemu,register
SUNW,bpp
SUNW,CS4231
SUNW,DBRI
SUNW,DBRI.prom
SUNW,fdtwo
SUNW,sx
SUNW,tcx
xilinx,zynq_slcr
xlnx,zynqmp
xlnx,zynqmp-pmu-soc
xlnx,zynq-xadc
These are all device types. They can't be plugged with -device /
device_add, except for xlnx,zynqmp-pmu-soc, and I doubt that one
actually works.
They *can* be used with -device / device_add to request help.
Usability is poor, though: you have to double the comma, like this:
$ qemu-system-x86_64 -device SUNW,,fdtwo,help
Trap for the unwary. The fact that this was broken in
device-introspect-test for more than six years until commit e27bd49876
fixed it demonstrates that "the unwary" includes seasoned developers.
One QOM type name contains ' ': "ICH9 SMB". Because having to
remember just one way to quote would be too easy.
Rename the "SUNW,FOO types to "sun-FOO". Summarily replace ',' and '
' by '-' in the other type names.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20210304140229.575481-2-armbru@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
2021-03-04 17:02:28 +03:00
|
|
|
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
|
2020-09-16 21:25:19 +03:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
|
2015-05-15 05:22:58 +03:00
|
|
|
|
2015-06-19 16:17:45 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_APU_CPUS 4
|
2015-06-19 16:17:45 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
|
2015-05-15 05:23:12 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_GEMS 4
|
2015-05-15 05:23:21 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_UARTS 2
|
2020-11-18 22:48:44 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_CAN 2
|
|
|
|
#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
|
2015-10-08 16:21:03 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_SDHCI 2
|
2016-01-21 17:15:03 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_SPIS 2
|
2018-05-18 19:48:07 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
|
|
|
|
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
|
2022-09-20 11:15:17 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_USB 2
|
2015-05-15 05:22:58 +03:00
|
|
|
|
2017-12-13 20:59:22 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
|
|
|
|
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
|
|
|
|
#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
|
|
|
|
|
2015-08-25 17:45:06 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
|
|
|
|
#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
|
|
|
|
#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
|
|
|
|
|
2018-08-14 19:17:21 +03:00
|
|
|
#define XLNX_ZYNQMP_GIC_REGIONS 6
|
2015-05-15 05:23:01 +03:00
|
|
|
|
2021-03-03 16:52:51 +03:00
|
|
|
/*
|
|
|
|
* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
|
2015-05-15 05:23:01 +03:00
|
|
|
* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
|
|
|
|
* aligned address in the 64k region. To implement each GIC region needs a
|
|
|
|
* number of memory region aliases.
|
|
|
|
*/
|
|
|
|
|
2015-09-14 16:39:47 +03:00
|
|
|
#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
|
2018-08-14 19:17:21 +03:00
|
|
|
#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
|
2015-05-15 05:23:01 +03:00
|
|
|
|
2016-01-13 01:39:18 +03:00
|
|
|
#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
|
|
|
|
|
|
|
|
#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
|
|
|
|
#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
|
|
|
|
|
|
|
|
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
|
|
|
|
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
|
|
|
|
|
2022-04-01 01:20:17 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_TTC 4
|
|
|
|
|
2021-08-23 20:38:18 +03:00
|
|
|
/*
|
|
|
|
* Unimplemented mmio regions needed to boot some images.
|
|
|
|
*/
|
2022-03-16 19:46:45 +03:00
|
|
|
#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
|
2021-08-23 20:38:18 +03:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct XlnxZynqMPState {
|
2015-05-15 05:22:58 +03:00
|
|
|
/*< private >*/
|
|
|
|
DeviceState parent_obj;
|
|
|
|
|
|
|
|
/*< public >*/
|
2019-01-07 18:23:46 +03:00
|
|
|
CPUClusterState apu_cluster;
|
|
|
|
CPUClusterState rpu_cluster;
|
2015-06-19 16:17:45 +03:00
|
|
|
ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
|
2015-06-19 16:17:45 +03:00
|
|
|
ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
|
2015-05-15 05:23:01 +03:00
|
|
|
GICState gic;
|
|
|
|
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
|
2016-01-13 01:39:18 +03:00
|
|
|
|
2015-08-25 17:45:06 +03:00
|
|
|
MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
|
|
|
|
|
2016-01-13 01:39:18 +03:00
|
|
|
MemoryRegion *ddr_ram;
|
|
|
|
MemoryRegion ddr_ram_low, ddr_ram_high;
|
2021-09-17 08:23:58 +03:00
|
|
|
XlnxBBRam bbram;
|
2021-09-17 08:23:59 +03:00
|
|
|
XlnxEFuse efuse;
|
|
|
|
XlnxZynqMPEFuse efuse_ctrl;
|
2016-01-13 01:39:18 +03:00
|
|
|
|
2021-08-23 20:38:18 +03:00
|
|
|
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
|
|
|
|
|
2015-05-15 05:23:12 +03:00
|
|
|
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
|
2015-05-15 05:23:21 +03:00
|
|
|
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
|
2020-11-18 22:48:44 +03:00
|
|
|
XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
|
2015-09-08 19:38:45 +03:00
|
|
|
SysbusAHCIState sata;
|
2015-10-08 16:21:03 +03:00
|
|
|
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
|
2016-01-21 17:15:03 +03:00
|
|
|
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
|
2017-12-13 20:59:22 +03:00
|
|
|
XlnxZynqMPQSPIPS qspi;
|
2016-06-14 17:59:15 +03:00
|
|
|
XlnxDPState dp;
|
|
|
|
XlnxDPDMAState dpdma;
|
2018-01-22 22:43:52 +03:00
|
|
|
XlnxZynqMPIPI ipi;
|
2018-03-02 13:45:35 +03:00
|
|
|
XlnxZynqMPRTC rtc;
|
2018-05-18 19:48:07 +03:00
|
|
|
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
|
|
|
|
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
|
2021-03-03 16:52:52 +03:00
|
|
|
XlnxCSUDMA qspi_dma;
|
2023-01-13 23:01:38 +03:00
|
|
|
OrIRQState qspi_irq_orgate;
|
2022-03-16 19:46:45 +03:00
|
|
|
XlnxZynqMPAPUCtrl apu_ctrl;
|
2022-03-16 19:46:43 +03:00
|
|
|
XlnxZynqMPCRF crf;
|
2022-04-01 01:20:17 +03:00
|
|
|
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
|
2022-09-20 11:15:17 +03:00
|
|
|
USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
|
2015-06-19 16:17:45 +03:00
|
|
|
|
|
|
|
char *boot_cpu;
|
|
|
|
ARMCPU *boot_cpu_ptr;
|
2016-06-06 18:59:29 +03:00
|
|
|
|
|
|
|
/* Has the ARM Security extensions? */
|
|
|
|
bool secure;
|
2017-09-14 20:43:18 +03:00
|
|
|
/* Has the ARM Virtualization extensions? */
|
|
|
|
bool virt;
|
2020-11-18 22:48:44 +03:00
|
|
|
|
|
|
|
/* CAN bus. */
|
|
|
|
CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2015-05-15 05:22:58 +03:00
|
|
|
|
|
|
|
#endif
|