2021-02-08 08:46:10 +03:00
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#!/usr/bin/env python3
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##
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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2021-02-08 08:46:10 +03:00
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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import hex_common
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##
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## Helpers for gen_helper_prototype
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##
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def_helper_types = {
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2023-03-20 12:25:33 +03:00
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"N": "s32",
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"O": "s32",
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"P": "s32",
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"M": "s32",
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"C": "s32",
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"R": "s32",
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"V": "ptr",
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"Q": "ptr",
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2021-02-08 08:46:10 +03:00
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}
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def_helper_types_pair = {
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2023-03-20 12:25:33 +03:00
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"R": "s64",
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"C": "s64",
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"S": "s64",
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"G": "s64",
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"V": "ptr",
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"Q": "ptr",
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2021-02-08 08:46:10 +03:00
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}
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i):
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2023-03-20 12:25:33 +03:00
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if hex_common.is_pair(regid):
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2023-03-20 12:25:32 +03:00
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f.write(f", {def_helper_types_pair[regtype]}")
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2023-03-20 12:25:33 +03:00
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elif hex_common.is_single(regid):
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2023-03-20 12:25:32 +03:00
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f.write(f", {def_helper_types[regtype]}")
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2021-02-08 08:46:10 +03:00
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else:
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2023-03-20 12:25:33 +03:00
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print("Bad register parse: ", regtype, regid, toss, numregs)
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2021-02-08 08:46:10 +03:00
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##
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## Generate the DEF_HELPER prototype for an instruction
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## For A2_add: Rd32=add(Rs32,Rt32)
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## We produce:
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## DEF_HELPER_3(A2_add, s32, env, s32, s32)
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##
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def gen_helper_prototype(f, tag, tagregs, tagimms):
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regs = tagregs[tag]
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imms = tagimms[tag]
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numresults = 0
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numscalarresults = 0
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numscalarreadwrite = 0
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2023-03-20 12:25:33 +03:00
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for regtype, regid, toss, numregs in regs:
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if hex_common.is_written(regid):
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2021-02-08 08:46:10 +03:00
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numresults += 1
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2023-03-20 12:25:33 +03:00
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if hex_common.is_scalar_reg(regtype):
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2021-02-08 08:46:10 +03:00
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numscalarresults += 1
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2023-03-20 12:25:33 +03:00
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if hex_common.is_readwrite(regid):
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if hex_common.is_scalar_reg(regtype):
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2021-02-08 08:46:10 +03:00
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numscalarreadwrite += 1
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2023-03-20 12:25:33 +03:00
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if numscalarresults > 1:
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2021-02-08 08:46:10 +03:00
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## The helper is bogus when there is more than one result
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2023-03-20 12:25:33 +03:00
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f.write(f"DEF_HELPER_1({tag}, void, env)\n")
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2021-02-08 08:46:10 +03:00
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else:
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## Figure out how many arguments the helper will take
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2023-03-20 12:25:33 +03:00
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if numscalarresults == 0:
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def_helper_size = len(regs) + len(imms) + numscalarreadwrite + 1
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if hex_common.need_pkt_has_multi_cof(tag):
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def_helper_size += 1
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Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
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if hex_common.need_pkt_need_commit(tag):
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def_helper_size += 1
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2023-03-20 12:25:33 +03:00
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if hex_common.need_part1(tag):
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def_helper_size += 1
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if hex_common.need_slot(tag):
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def_helper_size += 1
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if hex_common.need_PC(tag):
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def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag):
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def_helper_size += 1
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if hex_common.need_condexec_reg(tag, regs):
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def_helper_size += 1
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f.write(f"DEF_HELPER_{def_helper_size}({tag}")
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2021-02-08 08:46:10 +03:00
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## The return type is void
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2023-03-20 12:25:33 +03:00
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f.write(", void")
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2021-02-08 08:46:10 +03:00
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else:
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2023-03-20 12:25:33 +03:00
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def_helper_size = len(regs) + len(imms) + numscalarreadwrite
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if hex_common.need_pkt_has_multi_cof(tag):
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def_helper_size += 1
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Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
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if hex_common.need_pkt_need_commit(tag):
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def_helper_size += 1
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2023-03-20 12:25:33 +03:00
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if hex_common.need_part1(tag):
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def_helper_size += 1
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if hex_common.need_slot(tag):
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def_helper_size += 1
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if hex_common.need_PC(tag):
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def_helper_size += 1
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if hex_common.need_condexec_reg(tag, regs):
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def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag):
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def_helper_size += 1
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f.write(f"DEF_HELPER_{def_helper_size}({tag}")
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2021-02-08 08:46:10 +03:00
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## Generate the qemu DEF_HELPER type for each result
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2020-12-10 03:35:22 +03:00
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## Iterate over this list twice
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## - Emit the scalar result
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## - Emit the vector result
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2023-03-20 12:25:33 +03:00
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i = 0
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for regtype, regid, toss, numregs in regs:
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if hex_common.is_written(regid):
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if not hex_common.is_hvx_reg(regtype):
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2020-12-10 03:35:22 +03:00
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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2021-02-08 08:46:10 +03:00
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i += 1
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## Put the env between the outputs and inputs
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2023-03-20 12:25:33 +03:00
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f.write(", env")
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2021-02-08 08:46:10 +03:00
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i += 1
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2020-12-10 03:35:22 +03:00
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# Second pass
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2023-03-20 12:25:33 +03:00
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for regtype, regid, toss, numregs in regs:
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if hex_common.is_written(regid):
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if hex_common.is_hvx_reg(regtype):
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2020-12-10 03:35:22 +03:00
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## For conditional instructions, we pass in the destination register
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2023-03-20 12:25:33 +03:00
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if "A_CONDEXEC" in hex_common.attribdict[tag]:
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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for regtype, regid, toss, numregs in regs:
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2023-03-20 12:25:33 +03:00
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if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
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regtype
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):
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
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2021-02-08 08:46:10 +03:00
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## Generate the qemu type for each input operand (regs and immediates)
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2023-03-20 12:25:33 +03:00
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for regtype, regid, toss, numregs in regs:
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if hex_common.is_read(regid):
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if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
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2020-12-10 03:35:22 +03:00
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continue
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2021-02-08 08:46:10 +03:00
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
|
2023-03-20 12:25:33 +03:00
|
|
|
for immlett, bits, immshift in imms:
|
2021-02-08 08:46:10 +03:00
|
|
|
f.write(", s32")
|
|
|
|
|
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
|
|
|
## Add the arguments for the instruction pkt_has_multi_cof,
|
|
|
|
## pkt_needs_commit, PC, next_PC, slot, and part1 (if needed)
|
2023-03-20 12:25:33 +03:00
|
|
|
if hex_common.need_pkt_has_multi_cof(tag):
|
|
|
|
f.write(", i32")
|
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
|
|
|
if hex_common.need_pkt_need_commit(tag):
|
|
|
|
f.write(', i32')
|
2023-03-20 12:25:33 +03:00
|
|
|
if hex_common.need_PC(tag):
|
|
|
|
f.write(", i32")
|
|
|
|
if hex_common.helper_needs_next_PC(tag):
|
|
|
|
f.write(", i32")
|
|
|
|
if hex_common.need_slot(tag):
|
|
|
|
f.write(", i32")
|
|
|
|
if hex_common.need_part1(tag):
|
|
|
|
f.write(" , i32")
|
|
|
|
f.write(")\n")
|
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
|
|
|
|
def main():
|
|
|
|
hex_common.read_semantics_file(sys.argv[1])
|
|
|
|
hex_common.read_attribs_file(sys.argv[2])
|
|
|
|
hex_common.read_overrides_file(sys.argv[3])
|
2021-05-18 20:01:09 +03:00
|
|
|
hex_common.read_overrides_file(sys.argv[4])
|
2022-09-23 20:38:30 +03:00
|
|
|
## Whether or not idef-parser is enabled is
|
|
|
|
## determined by the number of arguments to
|
|
|
|
## this script:
|
|
|
|
##
|
|
|
|
## 5 args. -> not enabled,
|
|
|
|
## 6 args. -> idef-parser enabled.
|
|
|
|
##
|
|
|
|
## The 6:th arg. then holds a list of the successfully
|
|
|
|
## parsed instructions.
|
|
|
|
is_idef_parser_enabled = len(sys.argv) > 6
|
|
|
|
if is_idef_parser_enabled:
|
|
|
|
hex_common.read_idef_parser_enabled_file(sys.argv[5])
|
2021-02-08 08:46:10 +03:00
|
|
|
hex_common.calculate_attribs()
|
|
|
|
tagregs = hex_common.get_tagregs()
|
|
|
|
tagimms = hex_common.get_tagimms()
|
|
|
|
|
2022-09-23 20:38:30 +03:00
|
|
|
output_file = sys.argv[-1]
|
2023-03-20 12:25:33 +03:00
|
|
|
with open(output_file, "w") as f:
|
2021-02-08 08:46:10 +03:00
|
|
|
for tag in hex_common.tags:
|
|
|
|
## Skip the priv instructions
|
2023-03-20 12:25:33 +03:00
|
|
|
if "A_PRIV" in hex_common.attribdict[tag]:
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
|
|
|
## Skip the guest instructions
|
2023-03-20 12:25:33 +03:00
|
|
|
if "A_GUEST" in hex_common.attribdict[tag]:
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
|
|
|
## Skip the diag instructions
|
2023-03-20 12:25:33 +03:00
|
|
|
if tag == "Y6_diag":
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
2023-03-20 12:25:33 +03:00
|
|
|
if tag == "Y6_diag0":
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
2023-03-20 12:25:33 +03:00
|
|
|
if tag == "Y6_diag1":
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
if hex_common.skip_qemu_helper(tag):
|
2021-02-08 08:46:10 +03:00
|
|
|
continue
|
2023-03-20 12:25:33 +03:00
|
|
|
if hex_common.is_idef_parser_enabled(tag):
|
2022-09-23 20:38:30 +03:00
|
|
|
continue
|
2021-02-08 08:46:10 +03:00
|
|
|
|
|
|
|
gen_helper_prototype(f, tag, tagregs, tagimms)
|
|
|
|
|
2023-03-20 12:25:33 +03:00
|
|
|
|
2021-02-08 08:46:10 +03:00
|
|
|
if __name__ == "__main__":
|
|
|
|
main()
|