2017-10-01 23:11:45 +03:00
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/*
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* QEMU HPPA hardware system emulator.
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* Copyright 2018 Helge Deller <deller@gmx.de>
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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2020-10-28 14:36:57 +03:00
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#include "qemu/datadir.h"
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2017-10-01 23:11:45 +03:00
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#include "cpu.h"
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#include "elf.h"
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#include "hw/loader.h"
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#include "hw/boards.h"
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#include "qemu/error-report.h"
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2019-08-12 08:23:38 +03:00
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#include "sysemu/reset.h"
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2017-10-01 23:11:45 +03:00
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#include "sysemu/sysemu.h"
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2020-08-26 18:45:43 +03:00
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#include "sysemu/runstate.h"
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2019-10-04 02:03:53 +03:00
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#include "hw/rtc/mc146818rtc.h"
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2017-10-01 23:11:45 +03:00
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#include "hw/timer/i8254.h"
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#include "hw/char/serial.h"
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2019-12-21 00:15:08 +03:00
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#include "hw/net/lasi_82596.h"
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2018-05-03 22:50:25 +03:00
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#include "hppa_sys.h"
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2018-06-25 15:42:11 +03:00
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#include "qemu/units.h"
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2017-10-01 23:11:45 +03:00
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#include "qapi/error.h"
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2019-12-12 19:15:43 +03:00
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#include "net/net.h"
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2018-02-04 09:41:41 +03:00
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#include "qemu/log.h"
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2020-02-28 14:46:40 +03:00
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#include "net/net.h"
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2017-10-01 23:11:45 +03:00
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2017-10-08 23:47:27 +03:00
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#define MAX_IDE_BUS 2
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2020-07-27 23:43:44 +03:00
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#define MIN_SEABIOS_HPPA_VERSION 1 /* require at least this fw version */
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2020-08-26 18:45:43 +03:00
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#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
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static void hppa_powerdown_req(Notifier *n, void *opaque)
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{
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hwaddr soft_power_reg = HPA_POWER_BUTTON;
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uint32_t val;
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val = ldl_be_phys(&address_space_memory, soft_power_reg);
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if ((val >> 8) == 0) {
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/* immediately shut down when under hardware control */
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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return;
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}
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/* clear bit 31 to indicate that the power switch was pressed. */
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val &= ~1;
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stl_be_phys(&address_space_memory, soft_power_reg, val);
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}
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static Notifier hppa_system_powerdown_notifier = {
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.notify = hppa_powerdown_req
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};
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2017-10-08 23:47:27 +03:00
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static ISABus *hppa_isa_bus(void)
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{
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ISABus *isa_bus;
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qemu_irq *isa_irqs;
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MemoryRegion *isa_region;
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isa_region = g_new(MemoryRegion, 1);
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memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops,
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NULL, "isa-io", 0x800);
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memory_region_add_subregion(get_system_memory(), IDE_HPA,
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isa_region);
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isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region,
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&error_abort);
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isa_irqs = i8259_init(isa_bus,
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/* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */
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NULL);
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isa_bus_irqs(isa_bus, isa_irqs);
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return isa_bus;
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}
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static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr)
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{
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addr &= (0x10000000 - 1);
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return addr;
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}
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static HPPACPU *cpu[HPPA_MAX_CPUS];
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static uint64_t firmware_entry;
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2017-10-01 23:11:45 +03:00
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2020-08-09 18:06:50 +03:00
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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2020-07-27 23:43:44 +03:00
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static FWCfgState *create_fw_cfg(MachineState *ms)
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{
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FWCfgState *fw_cfg;
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uint64_t val;
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2020-09-02 22:21:01 +03:00
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fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4);
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2020-07-27 23:43:44 +03:00
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
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2020-10-28 13:19:23 +03:00
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
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2020-07-27 23:43:44 +03:00
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val = cpu_to_le64(MIN_SEABIOS_HPPA_VERSION);
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fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2020-08-27 14:10:32 +03:00
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val = cpu_to_le64(HPPA_TLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPPA_BTLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2020-08-26 18:45:43 +03:00
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val = cpu_to_le64(HPA_POWER_BUTTON);
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fw_cfg_add_file(fw_cfg, "/etc/power-button-addr",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2020-08-09 18:06:50 +03:00
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fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ms->boot_order[0]);
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qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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2020-07-27 23:43:44 +03:00
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return fw_cfg;
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}
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2017-10-01 23:11:45 +03:00
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static void machine_hppa_init(MachineState *machine)
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{
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2017-10-08 23:47:27 +03:00
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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2018-09-19 20:20:58 +03:00
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DeviceState *dev;
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2017-10-08 23:47:27 +03:00
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PCIBus *pci_bus;
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ISABus *isa_bus;
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qemu_irq rtc_irq, serial_irq;
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char *firmware_filename;
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uint64_t firmware_low, firmware_high;
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long size;
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uint64_t kernel_entry = 0, kernel_low, kernel_high;
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MemoryRegion *addr_space = get_system_memory();
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MemoryRegion *rom_region;
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MemoryRegion *cpu_region;
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long i;
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2019-05-18 23:54:27 +03:00
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unsigned int smp_cpus = machine->smp.cpus;
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2019-12-21 00:15:11 +03:00
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SysBusDevice *s;
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2017-10-08 23:47:27 +03:00
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/* Create CPUs. */
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for (i = 0; i < smp_cpus; i++) {
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2019-10-01 16:36:24 +03:00
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char *name = g_strdup_printf("cpu%ld-io-eir", i);
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2017-10-08 23:47:27 +03:00
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cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type));
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cpu_region = g_new(MemoryRegion, 1);
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memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops,
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2019-10-01 16:36:24 +03:00
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cpu[i], name, 4);
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2017-10-08 23:47:27 +03:00
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memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000,
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cpu_region);
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2019-10-01 16:36:24 +03:00
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g_free(name);
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2017-10-08 23:47:27 +03:00
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}
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/* Main memory region. */
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2020-01-09 03:05:24 +03:00
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if (machine->ram_size > 3 * GiB) {
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error_report("RAM size is currently restricted to 3GB");
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exit(EXIT_FAILURE);
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}
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2020-02-19 19:09:15 +03:00
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memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1);
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2017-10-08 23:47:27 +03:00
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2019-12-21 00:15:08 +03:00
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/* Init Lasi chip */
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lasi_init(addr_space);
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2017-10-08 23:47:27 +03:00
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/* Init Dino (PCI host bus chip). */
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pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq);
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assert(pci_bus);
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/* Create ISA bus. */
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isa_bus = hppa_isa_bus();
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assert(isa_bus);
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/* Realtime clock, used by firmware for PDC_TOD call. */
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mc146818_rtc_init(isa_bus, 2000, rtc_irq);
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/* Serial code setup. */
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2018-04-20 17:52:43 +03:00
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if (serial_hd(0)) {
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2017-10-08 23:47:27 +03:00
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uint32_t addr = DINO_UART_HPA + 0x800;
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serial_mm_init(addr_space, addr, 0, serial_irq,
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2018-04-20 17:52:43 +03:00
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115200, serial_hd(0), DEVICE_BIG_ENDIAN);
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2017-10-08 23:47:27 +03:00
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}
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2020-07-27 23:43:44 +03:00
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/* fw_cfg configuration interface */
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create_fw_cfg(machine);
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2017-10-08 23:47:27 +03:00
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/* SCSI disk setup. */
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2018-09-19 20:20:58 +03:00
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dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
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lsi53c8xx_handle_legacy_cmdline(dev);
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2017-10-08 23:47:27 +03:00
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2019-12-21 00:15:11 +03:00
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/* Graphics setup. */
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if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
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qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
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dev = qdev_new("artist");
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2019-12-21 00:15:11 +03:00
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s = SYS_BUS_DEVICE(dev);
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sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:32:34 +03:00
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sysbus_realize_and_unref(s, &error_fatal);
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2019-12-21 00:15:11 +03:00
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sysbus_mmio_map(s, 0, LASI_GFX_HPA);
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sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);
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}
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2019-12-22 01:25:30 +03:00
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/* Network setup. */
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2017-10-08 23:47:27 +03:00
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for (i = 0; i < nb_nics; i++) {
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2019-12-21 00:15:08 +03:00
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if (!enable_lasi_lan()) {
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2019-12-22 01:25:30 +03:00
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pci_nic_init_nofail(&nd_table[i], pci_bus, "tulip", NULL);
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2019-12-21 00:15:08 +03:00
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}
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2017-10-08 23:47:27 +03:00
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}
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2020-08-26 18:45:43 +03:00
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/* register power switch emulation */
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qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier);
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2017-10-08 23:47:27 +03:00
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/* Load firmware. Given that this is not "real" firmware,
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but one explicitly written for the emulation, we might as
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well load it directly from an ELF image. */
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firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
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2020-10-26 17:30:17 +03:00
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machine->firmware ?: "hppa-firmware.img");
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2017-10-08 23:47:27 +03:00
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if (firmware_filename == NULL) {
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error_report("no firmware provided");
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exit(1);
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}
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2019-01-15 15:18:03 +03:00
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size = load_elf(firmware_filename, NULL, NULL, NULL,
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2020-01-27 01:55:04 +03:00
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&firmware_entry, &firmware_low, &firmware_high, NULL,
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2017-10-08 23:47:27 +03:00
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true, EM_PARISC, 0, 0);
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/* Unfortunately, load_elf sign-extends reading elf32. */
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firmware_entry = (target_ureg)firmware_entry;
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firmware_low = (target_ureg)firmware_low;
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firmware_high = (target_ureg)firmware_high;
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if (size < 0) {
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error_report("could not load firmware '%s'", firmware_filename);
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exit(1);
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}
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2018-02-04 09:41:41 +03:00
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qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64
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|
|
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n",
|
|
|
|
firmware_low, firmware_high, firmware_entry);
|
2020-01-09 03:05:23 +03:00
|
|
|
if (firmware_low < FIRMWARE_START || firmware_high >= FIRMWARE_END) {
|
2017-10-08 23:47:27 +03:00
|
|
|
error_report("Firmware overlaps with memory or IO space");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
g_free(firmware_filename);
|
|
|
|
|
|
|
|
rom_region = g_new(MemoryRegion, 1);
|
2019-10-08 14:33:18 +03:00
|
|
|
memory_region_init_ram(rom_region, NULL, "firmware",
|
|
|
|
(FIRMWARE_END - FIRMWARE_START), &error_fatal);
|
2017-10-08 23:47:27 +03:00
|
|
|
memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region);
|
|
|
|
|
|
|
|
/* Load kernel */
|
|
|
|
if (kernel_filename) {
|
2019-01-15 15:18:03 +03:00
|
|
|
size = load_elf(kernel_filename, NULL, &cpu_hppa_to_phys,
|
2020-01-27 01:55:04 +03:00
|
|
|
NULL, &kernel_entry, &kernel_low, &kernel_high, NULL,
|
2017-10-08 23:47:27 +03:00
|
|
|
true, EM_PARISC, 0, 0);
|
|
|
|
|
|
|
|
/* Unfortunately, load_elf sign-extends reading elf32. */
|
|
|
|
kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry);
|
|
|
|
kernel_low = (target_ureg)kernel_low;
|
|
|
|
kernel_high = (target_ureg)kernel_high;
|
|
|
|
|
|
|
|
if (size < 0) {
|
|
|
|
error_report("could not load kernel '%s'", kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
2018-02-04 09:41:41 +03:00
|
|
|
qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64
|
|
|
|
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64
|
2018-06-25 15:42:11 +03:00
|
|
|
", size %" PRIu64 " kB\n",
|
|
|
|
kernel_low, kernel_high, kernel_entry, size / KiB);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
if (kernel_cmdline) {
|
|
|
|
cpu[0]->env.gr[24] = 0x4000;
|
|
|
|
pstrcpy_targphys("cmdline", cpu[0]->env.gr[24],
|
|
|
|
TARGET_PAGE_SIZE, kernel_cmdline);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (initrd_filename) {
|
|
|
|
ram_addr_t initrd_base;
|
2018-09-13 13:07:13 +03:00
|
|
|
int64_t initrd_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
initrd_size = get_image_size(initrd_filename);
|
|
|
|
if (initrd_size < 0) {
|
|
|
|
error_report("could not load initial ram disk '%s'",
|
|
|
|
initrd_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Load the initrd image high in memory.
|
|
|
|
Mirror the algorithm used by palo:
|
|
|
|
(1) Due to sign-extension problems and PDC,
|
|
|
|
put the initrd no higher than 1G.
|
|
|
|
(2) Reserve 64k for stack. */
|
2020-10-28 13:19:23 +03:00
|
|
|
initrd_base = MIN(machine->ram_size, 1 * GiB);
|
2018-06-25 15:42:11 +03:00
|
|
|
initrd_base = initrd_base - 64 * KiB;
|
2017-10-08 23:47:27 +03:00
|
|
|
initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
|
|
|
|
|
|
|
|
if (initrd_base < kernel_high) {
|
|
|
|
error_report("kernel and initial ram disk too large!");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
load_image_targphys(initrd_filename, initrd_base, initrd_size);
|
|
|
|
cpu[0]->env.gr[23] = initrd_base;
|
|
|
|
cpu[0]->env.gr[22] = initrd_base + initrd_size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!kernel_entry) {
|
|
|
|
/* When booting via firmware, tell firmware if we want interactive
|
|
|
|
* mode (kernel_entry=1), and to boot from CD (gr[24]='d')
|
|
|
|
* or hard disc * (gr[24]='c').
|
|
|
|
*/
|
|
|
|
kernel_entry = boot_menu ? 1 : 0;
|
|
|
|
cpu[0]->env.gr[24] = machine->boot_order[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We jump to the firmware entry routine and pass the
|
|
|
|
* various parameters in registers. After firmware initialization,
|
|
|
|
* firmware will start the Linux kernel with ramdisk and cmdline.
|
|
|
|
*/
|
2020-10-28 13:19:23 +03:00
|
|
|
cpu[0]->env.gr[26] = machine->ram_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu[0]->env.gr[25] = kernel_entry;
|
|
|
|
|
|
|
|
/* tell firmware how many SMP CPUs to present in inventory table */
|
|
|
|
cpu[0]->env.gr[21] = smp_cpus;
|
2020-09-02 22:21:01 +03:00
|
|
|
|
|
|
|
/* tell firmware fw_cfg port */
|
|
|
|
cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
|
2017-10-01 23:11:45 +03:00
|
|
|
}
|
|
|
|
|
2019-05-18 23:54:20 +03:00
|
|
|
static void hppa_machine_reset(MachineState *ms)
|
2017-10-08 23:47:27 +03:00
|
|
|
{
|
2019-05-18 23:54:27 +03:00
|
|
|
unsigned int smp_cpus = ms->smp.cpus;
|
2017-10-08 23:47:27 +03:00
|
|
|
int i;
|
|
|
|
|
|
|
|
qemu_devices_reset();
|
|
|
|
|
|
|
|
/* Start all CPUs at the firmware entry point.
|
|
|
|
* Monarch CPU will initialize firmware, secondary CPUs
|
|
|
|
* will enter a small idle look and wait for rendevouz. */
|
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
|
|
cpu_set_pc(CPU(cpu[i]), firmware_entry);
|
|
|
|
cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* already initialized by machine_hppa_init()? */
|
2020-10-28 13:19:23 +03:00
|
|
|
if (cpu[0]->env.gr[26] == ms->ram_size) {
|
2017-10-08 23:47:27 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-10-28 13:19:23 +03:00
|
|
|
cpu[0]->env.gr[26] = ms->ram_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu[0]->env.gr[25] = 0; /* no firmware boot menu */
|
|
|
|
cpu[0]->env.gr[24] = 'c';
|
|
|
|
/* gr22/gr23 unused, no initrd while reboot. */
|
|
|
|
cpu[0]->env.gr[21] = smp_cpus;
|
2020-09-02 22:21:01 +03:00
|
|
|
/* tell firmware fw_cfg port */
|
|
|
|
cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
|
2017-10-08 23:47:27 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-10-01 23:11:45 +03:00
|
|
|
static void machine_hppa_machine_init(MachineClass *mc)
|
|
|
|
{
|
|
|
|
mc->desc = "HPPA generic machine";
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->default_cpu_type = TYPE_HPPA_CPU;
|
2017-10-01 23:11:45 +03:00
|
|
|
mc->init = machine_hppa_init;
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->reset = hppa_machine_reset;
|
2017-10-01 23:11:45 +03:00
|
|
|
mc->block_default_type = IF_SCSI;
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->max_cpus = HPPA_MAX_CPUS;
|
|
|
|
mc->default_cpus = 1;
|
2020-02-07 19:19:47 +03:00
|
|
|
mc->is_default = true;
|
2018-06-25 15:41:57 +03:00
|
|
|
mc->default_ram_size = 512 * MiB;
|
2017-10-01 23:11:45 +03:00
|
|
|
mc->default_boot_order = "cd";
|
2020-02-19 19:09:15 +03:00
|
|
|
mc->default_ram_id = "ram";
|
2017-10-01 23:11:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
DEFINE_MACHINE("hppa", machine_hppa_machine_init)
|