2014-07-11 14:51:43 +04:00
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/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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2016-01-26 21:17:07 +03:00
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#include "qemu/osdep.h"
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2014-07-11 14:51:43 +04:00
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#include "qemu-common.h"
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#include "qemu/iov.h"
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#include "trace.h"
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#include "hw/virtio/virtio.h"
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#include "hw/virtio/virtio-gpu.h"
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2016-05-19 13:25:56 +03:00
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#include "qapi/error.h"
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2014-07-11 14:51:43 +04:00
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#ifdef CONFIG_VIRGL
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2016-06-22 20:11:19 +03:00
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#include <virglrenderer.h>
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2014-07-11 14:51:43 +04:00
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static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
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static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_create_2d c2d;
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struct virgl_renderer_resource_create_args args;
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VIRTIO_GPU_FILL_CMD(c2d);
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trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
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c2d.width, c2d.height);
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args.handle = c2d.resource_id;
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args.target = 2;
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args.format = c2d.format;
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args.bind = (1 << 1);
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args.width = c2d.width;
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args.height = c2d.height;
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args.depth = 1;
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args.array_size = 1;
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args.last_level = 0;
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args.nr_samples = 0;
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args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
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virgl_renderer_resource_create(&args, NULL, 0);
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}
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static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_create_3d c3d;
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struct virgl_renderer_resource_create_args args;
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VIRTIO_GPU_FILL_CMD(c3d);
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trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
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c3d.width, c3d.height, c3d.depth);
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args.handle = c3d.resource_id;
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args.target = c3d.target;
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args.format = c3d.format;
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args.bind = c3d.bind;
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args.width = c3d.width;
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args.height = c3d.height;
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args.depth = c3d.depth;
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args.array_size = c3d.array_size;
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args.last_level = c3d.last_level;
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args.nr_samples = c3d.nr_samples;
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args.flags = c3d.flags;
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virgl_renderer_resource_create(&args, NULL, 0);
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}
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static void virgl_cmd_resource_unref(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_unref unref;
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VIRTIO_GPU_FILL_CMD(unref);
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trace_virtio_gpu_cmd_res_unref(unref.resource_id);
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virgl_renderer_resource_unref(unref.resource_id);
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}
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static void virgl_cmd_context_create(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_ctx_create cc;
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VIRTIO_GPU_FILL_CMD(cc);
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trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
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cc.debug_name);
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virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
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cc.debug_name);
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}
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static void virgl_cmd_context_destroy(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_ctx_destroy cd;
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VIRTIO_GPU_FILL_CMD(cd);
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trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
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virgl_renderer_context_destroy(cd.hdr.ctx_id);
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}
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static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
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int width, int height)
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{
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if (!g->scanout[idx].con) {
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return;
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}
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dpy_gl_update(g->scanout[idx].con, x, y, width, height);
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}
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static void virgl_cmd_resource_flush(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_flush rf;
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int i;
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VIRTIO_GPU_FILL_CMD(rf);
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trace_virtio_gpu_cmd_res_flush(rf.resource_id,
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rf.r.width, rf.r.height, rf.r.x, rf.r.y);
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2016-05-19 13:25:58 +03:00
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for (i = 0; i < g->conf.max_outputs; i++) {
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2014-07-11 14:51:43 +04:00
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if (g->scanout[i].resource_id != rf.resource_id) {
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continue;
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}
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virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
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}
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}
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static void virgl_cmd_set_scanout(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_set_scanout ss;
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struct virgl_renderer_resource_info info;
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int ret;
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VIRTIO_GPU_FILL_CMD(ss);
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trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
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ss.r.width, ss.r.height, ss.r.x, ss.r.y);
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2016-05-19 13:25:58 +03:00
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if (ss.scanout_id >= g->conf.max_outputs) {
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2014-07-11 14:51:43 +04:00
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qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
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__func__, ss.scanout_id);
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cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
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return;
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}
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g->enable = 1;
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memset(&info, 0, sizeof(info));
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if (ss.resource_id && ss.r.width && ss.r.height) {
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ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
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if (ret == -1) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: illegal resource specified %d\n",
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__func__, ss.resource_id);
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cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
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return;
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}
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qemu_console_resize(g->scanout[ss.scanout_id].con,
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ss.r.width, ss.r.height);
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virgl_renderer_force_ctx_0();
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dpy_gl_scanout(g->scanout[ss.scanout_id].con, info.tex_id,
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info.flags & 1 /* FIXME: Y_0_TOP */,
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2016-06-14 16:44:09 +03:00
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info.width, info.height,
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2014-07-11 14:51:43 +04:00
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ss.r.x, ss.r.y, ss.r.width, ss.r.height);
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} else {
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if (ss.scanout_id != 0) {
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dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
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}
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dpy_gl_scanout(g->scanout[ss.scanout_id].con, 0, false,
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2016-06-14 16:44:09 +03:00
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0, 0, 0, 0, 0, 0);
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2014-07-11 14:51:43 +04:00
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}
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g->scanout[ss.scanout_id].resource_id = ss.resource_id;
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}
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static void virgl_cmd_submit_3d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_cmd_submit cs;
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void *buf;
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size_t s;
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VIRTIO_GPU_FILL_CMD(cs);
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trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
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buf = g_malloc(cs.size);
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s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
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sizeof(cs), buf, cs.size);
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if (s != cs.size) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
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__func__, s, cs.size);
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cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
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2015-12-18 13:55:01 +03:00
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goto out;
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2014-07-11 14:51:43 +04:00
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}
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if (virtio_gpu_stats_enabled(g->conf)) {
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g->stats.req_3d++;
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g->stats.bytes_3d += cs.size;
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}
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virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
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2015-12-18 13:55:01 +03:00
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out:
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2014-07-11 14:51:43 +04:00
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g_free(buf);
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}
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static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_transfer_to_host_2d t2d;
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struct virtio_gpu_box box;
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VIRTIO_GPU_FILL_CMD(t2d);
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trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
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box.x = t2d.r.x;
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box.y = t2d.r.y;
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box.z = 0;
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box.w = t2d.r.width;
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box.h = t2d.r.height;
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box.d = 1;
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virgl_renderer_transfer_write_iov(t2d.resource_id,
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0,
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0,
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0,
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0,
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(struct virgl_box *)&box,
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t2d.offset, NULL, 0);
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}
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static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_transfer_host_3d t3d;
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VIRTIO_GPU_FILL_CMD(t3d);
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trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
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virgl_renderer_transfer_write_iov(t3d.resource_id,
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t3d.hdr.ctx_id,
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t3d.level,
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t3d.stride,
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t3d.layer_stride,
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(struct virgl_box *)&t3d.box,
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t3d.offset, NULL, 0);
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}
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static void
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virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_transfer_host_3d tf3d;
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VIRTIO_GPU_FILL_CMD(tf3d);
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trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
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virgl_renderer_transfer_read_iov(tf3d.resource_id,
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tf3d.hdr.ctx_id,
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tf3d.level,
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tf3d.stride,
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tf3d.layer_stride,
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(struct virgl_box *)&tf3d.box,
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tf3d.offset, NULL, 0);
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}
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static void virgl_resource_attach_backing(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_attach_backing att_rb;
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struct iovec *res_iovs;
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int ret;
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VIRTIO_GPU_FILL_CMD(att_rb);
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trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
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2016-05-23 16:22:07 +03:00
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ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, NULL, &res_iovs);
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2014-07-11 14:51:43 +04:00
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if (ret != 0) {
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cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
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return;
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}
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virgl_renderer_resource_attach_iov(att_rb.resource_id,
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res_iovs, att_rb.nr_entries);
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}
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static void virgl_resource_detach_backing(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_detach_backing detach_rb;
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struct iovec *res_iovs = NULL;
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int num_iovs = 0;
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VIRTIO_GPU_FILL_CMD(detach_rb);
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trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
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virgl_renderer_resource_detach_iov(detach_rb.resource_id,
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&res_iovs,
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&num_iovs);
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if (res_iovs == NULL || num_iovs == 0) {
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return;
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}
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virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
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}
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static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_ctx_resource att_res;
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VIRTIO_GPU_FILL_CMD(att_res);
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trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
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att_res.resource_id);
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virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
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}
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static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_ctx_resource det_res;
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VIRTIO_GPU_FILL_CMD(det_res);
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|
|
trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
|
|
|
|
det_res.resource_id);
|
|
|
|
|
|
|
|
virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virgl_cmd_get_capset_info(VirtIOGPU *g,
|
|
|
|
struct virtio_gpu_ctrl_command *cmd)
|
|
|
|
{
|
|
|
|
struct virtio_gpu_get_capset_info info;
|
|
|
|
struct virtio_gpu_resp_capset_info resp;
|
|
|
|
|
|
|
|
VIRTIO_GPU_FILL_CMD(info);
|
|
|
|
|
2016-11-01 12:53:11 +03:00
|
|
|
memset(&resp, 0, sizeof(resp));
|
2014-07-11 14:51:43 +04:00
|
|
|
if (info.capset_index == 0) {
|
|
|
|
resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
|
|
|
|
virgl_renderer_get_cap_set(resp.capset_id,
|
|
|
|
&resp.capset_max_version,
|
|
|
|
&resp.capset_max_size);
|
|
|
|
} else {
|
|
|
|
resp.capset_max_version = 0;
|
|
|
|
resp.capset_max_size = 0;
|
|
|
|
}
|
|
|
|
resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
|
|
|
|
virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virgl_cmd_get_capset(VirtIOGPU *g,
|
|
|
|
struct virtio_gpu_ctrl_command *cmd)
|
|
|
|
{
|
|
|
|
struct virtio_gpu_get_capset gc;
|
|
|
|
struct virtio_gpu_resp_capset *resp;
|
|
|
|
uint32_t max_ver, max_size;
|
|
|
|
VIRTIO_GPU_FILL_CMD(gc);
|
|
|
|
|
|
|
|
virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
|
|
|
|
&max_size);
|
|
|
|
resp = g_malloc(sizeof(*resp) + max_size);
|
|
|
|
|
|
|
|
resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
|
|
|
|
virgl_renderer_fill_caps(gc.capset_id,
|
|
|
|
gc.capset_version,
|
|
|
|
(void *)resp->capset_data);
|
|
|
|
virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
|
|
|
|
g_free(resp);
|
|
|
|
}
|
|
|
|
|
|
|
|
void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
|
|
|
|
struct virtio_gpu_ctrl_command *cmd)
|
|
|
|
{
|
|
|
|
VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
|
|
|
|
|
2015-12-02 10:17:24 +03:00
|
|
|
cmd->waiting = g->renderer_blocked;
|
|
|
|
if (cmd->waiting) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-07-11 14:51:43 +04:00
|
|
|
virgl_renderer_force_ctx_0();
|
|
|
|
switch (cmd->cmd_hdr.type) {
|
|
|
|
case VIRTIO_GPU_CMD_CTX_CREATE:
|
|
|
|
virgl_cmd_context_create(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_CTX_DESTROY:
|
|
|
|
virgl_cmd_context_destroy(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
|
|
|
|
virgl_cmd_create_resource_2d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
|
|
|
|
virgl_cmd_create_resource_3d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_SUBMIT_3D:
|
|
|
|
virgl_cmd_submit_3d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
|
|
|
|
virgl_cmd_transfer_to_host_2d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
|
|
|
|
virgl_cmd_transfer_to_host_3d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
|
|
|
|
virgl_cmd_transfer_from_host_3d(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
|
|
|
|
virgl_resource_attach_backing(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
|
|
|
|
virgl_resource_detach_backing(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_SET_SCANOUT:
|
|
|
|
virgl_cmd_set_scanout(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
|
|
|
|
virgl_cmd_resource_flush(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_RESOURCE_UNREF:
|
|
|
|
virgl_cmd_resource_unref(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
|
|
|
|
/* TODO add security */
|
|
|
|
virgl_cmd_ctx_attach_resource(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
|
|
|
|
/* TODO add security */
|
|
|
|
virgl_cmd_ctx_detach_resource(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
|
|
|
|
virgl_cmd_get_capset_info(g, cmd);
|
|
|
|
break;
|
|
|
|
case VIRTIO_GPU_CMD_GET_CAPSET:
|
|
|
|
virgl_cmd_get_capset(g, cmd);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
|
|
|
|
virtio_gpu_get_display_info(g, cmd);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd->finished) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (cmd->error) {
|
|
|
|
fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
|
|
|
|
cmd->cmd_hdr.type, cmd->error);
|
|
|
|
virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
|
|
|
|
virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
|
|
|
|
virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virgl_write_fence(void *opaque, uint32_t fence)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
struct virtio_gpu_ctrl_command *cmd, *tmp;
|
|
|
|
|
|
|
|
QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
|
|
|
|
/*
|
|
|
|
* the guest can end up emitting fences out of order
|
|
|
|
* so we should check all fenced cmds not just the first one.
|
|
|
|
*/
|
|
|
|
if (cmd->cmd_hdr.fence_id > fence) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
|
|
|
|
virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
|
|
|
|
QTAILQ_REMOVE(&g->fenceq, cmd, next);
|
|
|
|
g_free(cmd);
|
|
|
|
g->inflight--;
|
|
|
|
if (virtio_gpu_stats_enabled(g->conf)) {
|
|
|
|
fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static virgl_renderer_gl_context
|
|
|
|
virgl_create_context(void *opaque, int scanout_idx,
|
|
|
|
struct virgl_renderer_gl_ctx_param *params)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
QEMUGLContext ctx;
|
|
|
|
QEMUGLParams qparams;
|
|
|
|
|
|
|
|
qparams.major_ver = params->major_ver;
|
|
|
|
qparams.minor_ver = params->minor_ver;
|
|
|
|
|
|
|
|
ctx = dpy_gl_ctx_create(g->scanout[scanout_idx].con, &qparams);
|
|
|
|
return (virgl_renderer_gl_context)ctx;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
QEMUGLContext qctx = (QEMUGLContext)ctx;
|
|
|
|
|
|
|
|
dpy_gl_ctx_destroy(g->scanout[0].con, qctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int virgl_make_context_current(void *opaque, int scanout_idx,
|
|
|
|
virgl_renderer_gl_context ctx)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
QEMUGLContext qctx = (QEMUGLContext)ctx;
|
|
|
|
|
|
|
|
return dpy_gl_ctx_make_current(g->scanout[scanout_idx].con, qctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
|
|
|
|
.version = 1,
|
|
|
|
.write_fence = virgl_write_fence,
|
|
|
|
.create_gl_context = virgl_create_context,
|
|
|
|
.destroy_gl_context = virgl_destroy_context,
|
|
|
|
.make_current = virgl_make_context_current,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void virtio_gpu_print_stats(void *opaque)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
|
|
|
|
if (g->stats.requests) {
|
|
|
|
fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
|
|
|
|
g->stats.requests,
|
|
|
|
g->stats.max_inflight,
|
|
|
|
g->stats.req_3d,
|
|
|
|
g->stats.bytes_3d);
|
|
|
|
g->stats.requests = 0;
|
|
|
|
g->stats.max_inflight = 0;
|
|
|
|
g->stats.req_3d = 0;
|
|
|
|
g->stats.bytes_3d = 0;
|
|
|
|
} else {
|
|
|
|
fprintf(stderr, "stats: idle\r");
|
|
|
|
}
|
|
|
|
timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virtio_gpu_fence_poll(void *opaque)
|
|
|
|
{
|
|
|
|
VirtIOGPU *g = opaque;
|
|
|
|
|
|
|
|
virgl_renderer_poll();
|
2015-12-01 15:18:38 +03:00
|
|
|
virtio_gpu_process_cmdq(g);
|
|
|
|
if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
|
2014-07-11 14:51:43 +04:00
|
|
|
timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
|
|
|
|
{
|
|
|
|
virtio_gpu_fence_poll(g);
|
|
|
|
}
|
|
|
|
|
|
|
|
void virtio_gpu_virgl_reset(VirtIOGPU *g)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* virgl_renderer_reset() ??? */
|
|
|
|
for (i = 0; i < g->conf.max_outputs; i++) {
|
|
|
|
if (i != 0) {
|
|
|
|
dpy_gfx_replace_surface(g->scanout[i].con, NULL);
|
|
|
|
}
|
2016-06-14 16:44:09 +03:00
|
|
|
dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0, 0, 0);
|
2014-07-11 14:51:43 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int virtio_gpu_virgl_init(VirtIOGPU *g)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
|
|
|
|
if (ret != 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
|
|
|
|
virtio_gpu_fence_poll, g);
|
|
|
|
|
|
|
|
if (virtio_gpu_stats_enabled(g->conf)) {
|
|
|
|
g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
|
|
|
|
virtio_gpu_print_stats, g);
|
|
|
|
timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_VIRGL */
|