2006-05-21 20:30:15 +04:00
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/*
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* QEMU USB OHCI Emulation
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* Copyright (c) 2004 Gianni Tedesco
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* Copyright (c) 2006 CodeSourcery
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2007-03-17 19:59:31 +03:00
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* Copyright (c) 2006 Openedhand Ltd.
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2006-05-21 20:30:15 +04:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2006-05-21 20:30:15 +04:00
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*
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* TODO:
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* o Isochronous transfers
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* o Allocate bandwidth in frames properly
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* o Disable timers when nothing needs to be done, or remove timer usage
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* all together.
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* o Handle unrecoverable errors properly
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* o BIOS work to boot from USB storage
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*/
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2007-11-17 20:14:51 +03:00
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#include "hw.h"
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#include "qemu-timer.h"
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#include "usb.h"
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#include "pci.h"
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2009-11-11 15:59:56 +03:00
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#include "usb-ohci.h"
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2010-04-05 22:57:40 +04:00
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#include "sysbus.h"
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#include "qdev-addr.h"
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2006-05-21 20:30:15 +04:00
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//#define DEBUG_OHCI
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/* Dump packet contents. */
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//#define DEBUG_PACKET
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2007-10-31 03:34:21 +03:00
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//#define DEBUG_ISOCH
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2006-05-21 20:30:15 +04:00
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
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#ifdef DEBUG_OHCI
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2010-02-07 02:03:50 +03:00
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#define DPRINTF printf
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2006-05-21 20:30:15 +04:00
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#else
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2010-02-07 02:03:50 +03:00
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#define DPRINTF(...)
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2006-05-21 20:30:15 +04:00
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#endif
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/* Number of Downstream Ports on the root hub. */
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#define OHCI_MAX_PORTS 15
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
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typedef struct OHCIPort {
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USBPort port;
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uint32_t ctrl;
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} OHCIPort;
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typedef struct {
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2009-09-17 00:25:29 +04:00
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USBBus bus;
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2007-04-07 22:14:41 +04:00
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qemu_irq irq;
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2011-07-26 15:26:22 +04:00
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MemoryRegion mem;
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2006-05-21 20:30:15 +04:00
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int num_ports;
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2007-03-17 19:59:31 +03:00
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const char *name;
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2006-05-21 20:30:15 +04:00
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QEMUTimer *eof_timer;
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int64_t sof_time;
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/* OHCI state */
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/* Control partition */
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uint32_t ctl, status;
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uint32_t intr_status;
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uint32_t intr;
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/* memory pointer partition */
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uint32_t hcca;
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uint32_t ctrl_head, ctrl_cur;
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uint32_t bulk_head, bulk_cur;
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uint32_t per_cur;
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uint32_t done;
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int done_count;
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/* Frame counter partition */
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uint32_t fsmps:15;
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uint32_t fit:1;
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uint32_t fi:14;
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uint32_t frt:1;
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uint16_t frame_number;
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uint16_t padding;
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uint32_t pstart;
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uint32_t lst;
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/* Root Hub partition */
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uint32_t rhdesc_a, rhdesc_b;
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uint32_t rhstatus;
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OHCIPort rhport[OHCI_MAX_PORTS];
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2006-08-12 05:04:27 +04:00
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2007-03-17 19:59:31 +03:00
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/* PXA27x Non-OHCI events */
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uint32_t hstatus;
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uint32_t hmask;
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uint32_t hreset;
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uint32_t htest;
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2009-04-19 13:15:50 +04:00
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/* SM501 local memory offset */
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2009-10-02 01:12:16 +04:00
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target_phys_addr_t localmem_base;
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2009-04-19 13:15:50 +04:00
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2006-08-12 05:04:27 +04:00
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/* Active packets. */
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uint32_t old_ctl;
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USBPacket usb_packet;
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uint8_t usb_buf[8192];
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uint32_t async_td;
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int async_complete;
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2006-05-21 20:30:15 +04:00
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} OHCIState;
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/* Host Controller Communications Area */
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struct ohci_hcca {
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uint32_t intr[32];
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uint16_t frame, pad;
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uint32_t done;
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};
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2007-07-25 20:50:37 +04:00
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static void ohci_bus_stop(OHCIState *ohci);
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2011-06-24 14:31:11 +04:00
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static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
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2007-07-25 20:50:37 +04:00
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2006-05-21 20:30:15 +04:00
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/* Bitfields for the first word of an Endpoint Desciptor. */
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#define OHCI_ED_FA_SHIFT 0
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#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
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#define OHCI_ED_EN_SHIFT 7
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#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
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#define OHCI_ED_D_SHIFT 11
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_S (1<<13)
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#define OHCI_ED_K (1<<14)
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#define OHCI_ED_F (1<<15)
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2007-10-31 03:34:21 +03:00
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
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2006-05-21 20:30:15 +04:00
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/* Flags in the head field of an Endpoint Desciptor. */
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#define OHCI_ED_H 1
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#define OHCI_ED_C 2
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/* Bitfields for the first word of a Transfer Desciptor. */
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#define OHCI_TD_R (1<<18)
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#define OHCI_TD_DP_SHIFT 19
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
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#define OHCI_TD_DI_SHIFT 21
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
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#define OHCI_TD_T0 (1<<24)
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#define OHCI_TD_T1 (1<<24)
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#define OHCI_TD_EC_SHIFT 26
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
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#define OHCI_TD_CC_SHIFT 28
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
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2007-10-31 03:34:21 +03:00
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/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
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/* CC & DI - same as in the General Transfer Desciptor */
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#define OHCI_TD_SF_SHIFT 0
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#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
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#define OHCI_TD_FC_SHIFT 24
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#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
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/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
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#define OHCI_TD_PSW_CC_SHIFT 12
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#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
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#define OHCI_TD_PSW_SIZE_SHIFT 0
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#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
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#define OHCI_PAGE_MASK 0xfffff000
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#define OHCI_OFFSET_MASK 0xfff
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2006-05-21 20:30:15 +04:00
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#define OHCI_DPTR_MASK 0xfffffff0
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
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#define OHCI_SET_BM(val, field, newval) do { \
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val &= ~OHCI_##field##_MASK; \
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
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} while(0)
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/* endpoint descriptor */
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struct ohci_ed {
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uint32_t flags;
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uint32_t tail;
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uint32_t head;
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uint32_t next;
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};
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/* General transfer descriptor */
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struct ohci_td {
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uint32_t flags;
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uint32_t cbp;
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uint32_t next;
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uint32_t be;
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};
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2007-10-31 03:34:21 +03:00
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/* Isochronous transfer descriptor */
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struct ohci_iso_td {
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uint32_t flags;
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uint32_t bp;
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uint32_t next;
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uint32_t be;
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uint16_t offset[8];
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};
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2006-05-21 20:30:15 +04:00
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#define USB_HZ 12000000
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/* OHCI Local stuff */
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#define OHCI_CTL_CBSR ((1<<0)|(1<<1))
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#define OHCI_CTL_PLE (1<<2)
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#define OHCI_CTL_IE (1<<3)
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#define OHCI_CTL_CLE (1<<4)
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#define OHCI_CTL_BLE (1<<5)
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#define OHCI_CTL_HCFS ((1<<6)|(1<<7))
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#define OHCI_USB_RESET 0x00
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#define OHCI_USB_RESUME 0x40
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#define OHCI_USB_OPERATIONAL 0x80
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#define OHCI_USB_SUSPEND 0xc0
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#define OHCI_CTL_IR (1<<8)
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#define OHCI_CTL_RWC (1<<9)
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#define OHCI_CTL_RWE (1<<10)
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#define OHCI_STATUS_HCR (1<<0)
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#define OHCI_STATUS_CLF (1<<1)
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#define OHCI_STATUS_BLF (1<<2)
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#define OHCI_STATUS_OCR (1<<3)
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#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
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#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
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#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
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#define OHCI_INTR_SF (1<<2) /* Start of frame */
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#define OHCI_INTR_RD (1<<3) /* Resume detect */
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#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
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#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
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#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
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#define OHCI_INTR_OC (1<<30) /* Ownership change */
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#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
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#define OHCI_HCCA_SIZE 0x100
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#define OHCI_HCCA_MASK 0xffffff00
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#define OHCI_EDPTR_MASK 0xfffffff0
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#define OHCI_FMI_FI 0x00003fff
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#define OHCI_FMI_FSMPS 0xffff0000
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#define OHCI_FMI_FIT 0x80000000
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#define OHCI_FR_RT (1<<31)
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#define OHCI_LS_THRESH 0x628
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#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
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#define OHCI_RHA_PSM (1<<8)
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#define OHCI_RHA_NPS (1<<9)
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#define OHCI_RHA_DT (1<<10)
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#define OHCI_RHA_OCPM (1<<11)
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#define OHCI_RHA_NOCP (1<<12)
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#define OHCI_RHA_POTPGT_MASK 0xff000000
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#define OHCI_RHS_LPS (1<<0)
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#define OHCI_RHS_OCI (1<<1)
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#define OHCI_RHS_DRWE (1<<15)
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#define OHCI_RHS_LPSC (1<<16)
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#define OHCI_RHS_OCIC (1<<17)
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#define OHCI_RHS_CRWE (1<<31)
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#define OHCI_PORT_CCS (1<<0)
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#define OHCI_PORT_PES (1<<1)
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#define OHCI_PORT_PSS (1<<2)
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#define OHCI_PORT_POCI (1<<3)
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#define OHCI_PORT_PRS (1<<4)
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#define OHCI_PORT_PPS (1<<8)
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#define OHCI_PORT_LSDA (1<<9)
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#define OHCI_PORT_CSC (1<<16)
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#define OHCI_PORT_PESC (1<<17)
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#define OHCI_PORT_PSSC (1<<18)
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#define OHCI_PORT_OCIC (1<<19)
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#define OHCI_PORT_PRSC (1<<20)
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#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
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|OHCI_PORT_OCIC|OHCI_PORT_PRSC)
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#define OHCI_TD_DIR_SETUP 0x0
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#define OHCI_TD_DIR_OUT 0x1
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#define OHCI_TD_DIR_IN 0x2
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#define OHCI_TD_DIR_RESERVED 0x3
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#define OHCI_CC_NOERROR 0x0
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#define OHCI_CC_CRC 0x1
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#define OHCI_CC_BITSTUFFING 0x2
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3
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#define OHCI_CC_STALL 0x4
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#define OHCI_CC_DEVICENOTRESPONDING 0x5
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#define OHCI_CC_PIDCHECKFAILURE 0x6
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#define OHCI_CC_UNDEXPETEDPID 0x7
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#define OHCI_CC_DATAOVERRUN 0x8
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#define OHCI_CC_DATAUNDERRUN 0x9
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#define OHCI_CC_BUFFEROVERRUN 0xc
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#define OHCI_CC_BUFFERUNDERRUN 0xd
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2007-03-17 19:59:31 +03:00
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#define OHCI_HRESET_FSBIR (1 << 0)
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2006-05-22 21:17:06 +04:00
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/* Update IRQ levels */
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static inline void ohci_intr_update(OHCIState *ohci)
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{
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int level = 0;
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if ((ohci->intr & OHCI_INTR_MIE) &&
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(ohci->intr_status & ohci->intr))
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level = 1;
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2007-04-07 22:14:41 +04:00
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qemu_set_irq(ohci->irq, level);
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2006-05-22 21:17:06 +04:00
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}
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/* Set an interrupt */
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static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
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{
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ohci->intr_status |= intr;
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ohci_intr_update(ohci);
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}
|
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|
|
|
|
|
|
/* Attach or detach a device on a root hub port. */
|
2010-12-01 13:27:05 +03:00
|
|
|
static void ohci_attach(USBPort *port1)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
OHCIState *s = port1->opaque;
|
|
|
|
OHCIPort *port = &s->rhport[port1->index];
|
2011-07-07 17:18:50 +04:00
|
|
|
uint32_t old_state = port->ctrl;
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2010-12-01 13:27:05 +03:00
|
|
|
/* set connect status */
|
|
|
|
port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
|
|
|
|
|
|
|
|
/* update speed */
|
|
|
|
if (port->port.dev->speed == USB_SPEED_LOW) {
|
|
|
|
port->ctrl |= OHCI_PORT_LSDA;
|
2006-05-21 20:30:15 +04:00
|
|
|
} else {
|
2010-12-01 13:27:05 +03:00
|
|
|
port->ctrl &= ~OHCI_PORT_LSDA;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* notify of remote-wakeup */
|
|
|
|
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
|
|
|
|
ohci_set_interrupt(s, OHCI_INTR_RD);
|
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF("usb-ohci: Attached port %d\n", port1->index);
|
2011-07-07 17:18:50 +04:00
|
|
|
|
|
|
|
if (old_state != port->ctrl) {
|
|
|
|
ohci_set_interrupt(s, OHCI_INTR_RHSC);
|
|
|
|
}
|
2010-12-01 13:27:05 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ohci_detach(USBPort *port1)
|
|
|
|
{
|
|
|
|
OHCIState *s = port1->opaque;
|
|
|
|
OHCIPort *port = &s->rhport[port1->index];
|
|
|
|
uint32_t old_state = port->ctrl;
|
|
|
|
|
2011-06-24 14:31:11 +04:00
|
|
|
ohci_async_cancel_device(s, port1->dev);
|
|
|
|
|
2010-12-01 13:27:05 +03:00
|
|
|
/* set connect status */
|
|
|
|
if (port->ctrl & OHCI_PORT_CCS) {
|
|
|
|
port->ctrl &= ~OHCI_PORT_CCS;
|
|
|
|
port->ctrl |= OHCI_PORT_CSC;
|
|
|
|
}
|
|
|
|
/* disable port */
|
|
|
|
if (port->ctrl & OHCI_PORT_PES) {
|
|
|
|
port->ctrl &= ~OHCI_PORT_PES;
|
|
|
|
port->ctrl |= OHCI_PORT_PESC;
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
2010-12-01 13:27:05 +03:00
|
|
|
DPRINTF("usb-ohci: Detached port %d\n", port1->index);
|
2006-05-22 21:17:06 +04:00
|
|
|
|
2011-07-07 17:18:50 +04:00
|
|
|
if (old_state != port->ctrl) {
|
2006-05-22 21:17:06 +04:00
|
|
|
ohci_set_interrupt(s, OHCI_INTR_RHSC);
|
2011-07-07 17:18:50 +04:00
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2011-06-21 13:52:28 +04:00
|
|
|
static void ohci_wakeup(USBPort *port1)
|
2011-06-07 22:50:12 +04:00
|
|
|
{
|
2011-06-21 13:52:28 +04:00
|
|
|
OHCIState *s = port1->opaque;
|
|
|
|
OHCIPort *port = &s->rhport[port1->index];
|
2011-06-15 21:22:35 +04:00
|
|
|
uint32_t intr = 0;
|
2011-06-07 22:50:12 +04:00
|
|
|
if (port->ctrl & OHCI_PORT_PSS) {
|
2011-06-21 13:52:28 +04:00
|
|
|
DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
|
2011-06-07 22:50:12 +04:00
|
|
|
port->ctrl |= OHCI_PORT_PSSC;
|
|
|
|
port->ctrl &= ~OHCI_PORT_PSS;
|
2011-06-15 21:22:35 +04:00
|
|
|
intr = OHCI_INTR_RHSC;
|
2011-06-07 22:50:12 +04:00
|
|
|
}
|
2011-06-15 21:22:35 +04:00
|
|
|
/* Note that the controller can be suspended even if this port is not */
|
|
|
|
if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
|
|
|
|
DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
|
|
|
|
/* This is the one state transition the controller can do by itself */
|
|
|
|
s->ctl &= ~OHCI_CTL_HCFS;
|
|
|
|
s->ctl |= OHCI_USB_RESUME;
|
|
|
|
/* In suspend mode only ResumeDetected is possible, not RHSC:
|
|
|
|
* see the OHCI spec 5.1.2.3.
|
|
|
|
*/
|
|
|
|
intr = OHCI_INTR_RD;
|
|
|
|
}
|
|
|
|
ohci_set_interrupt(s, intr);
|
2011-06-07 22:50:12 +04:00
|
|
|
}
|
|
|
|
|
2011-06-24 14:31:11 +04:00
|
|
|
static void ohci_child_detach(USBPort *port1, USBDevice *child)
|
|
|
|
{
|
|
|
|
OHCIState *s = port1->opaque;
|
|
|
|
|
|
|
|
ohci_async_cancel_device(s, child);
|
|
|
|
}
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
/* Reset the controller */
|
2007-07-25 20:50:37 +04:00
|
|
|
static void ohci_reset(void *opaque)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2007-07-25 20:50:37 +04:00
|
|
|
OHCIState *ohci = opaque;
|
2006-05-21 20:30:15 +04:00
|
|
|
OHCIPort *port;
|
|
|
|
int i;
|
|
|
|
|
2007-07-25 20:50:37 +04:00
|
|
|
ohci_bus_stop(ohci);
|
2006-05-21 20:30:15 +04:00
|
|
|
ohci->ctl = 0;
|
2006-08-12 05:04:27 +04:00
|
|
|
ohci->old_ctl = 0;
|
2006-05-21 20:30:15 +04:00
|
|
|
ohci->status = 0;
|
|
|
|
ohci->intr_status = 0;
|
|
|
|
ohci->intr = OHCI_INTR_MIE;
|
|
|
|
|
|
|
|
ohci->hcca = 0;
|
|
|
|
ohci->ctrl_head = ohci->ctrl_cur = 0;
|
|
|
|
ohci->bulk_head = ohci->bulk_cur = 0;
|
|
|
|
ohci->per_cur = 0;
|
|
|
|
ohci->done = 0;
|
|
|
|
ohci->done_count = 7;
|
|
|
|
|
|
|
|
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
|
|
|
|
* I took the value linux sets ...
|
|
|
|
*/
|
|
|
|
ohci->fsmps = 0x2778;
|
|
|
|
ohci->fi = 0x2edf;
|
|
|
|
ohci->fit = 0;
|
|
|
|
ohci->frt = 0;
|
|
|
|
ohci->frame_number = 0;
|
|
|
|
ohci->pstart = 0;
|
|
|
|
ohci->lst = OHCI_LS_THRESH;
|
|
|
|
|
|
|
|
ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
|
|
|
|
ohci->rhdesc_b = 0x0; /* Impl. specific */
|
|
|
|
ohci->rhstatus = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ohci->num_ports; i++)
|
|
|
|
{
|
|
|
|
port = &ohci->rhport[i];
|
|
|
|
port->ctrl = 0;
|
2011-09-01 15:56:37 +04:00
|
|
|
if (port->port.dev && port->port.dev->attached) {
|
|
|
|
usb_attach(&port->port);
|
2010-12-01 13:27:05 +03:00
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
2006-08-12 05:04:27 +04:00
|
|
|
if (ohci->async_td) {
|
|
|
|
usb_cancel_packet(&ohci->usb_packet);
|
|
|
|
ohci->async_td = 0;
|
|
|
|
}
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: Reset %s\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Get an array of dwords from main memory */
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int get_dwords(OHCIState *ohci,
|
|
|
|
uint32_t addr, uint32_t *buf, int num)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
addr += ohci->localmem_base;
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_read(addr, buf, sizeof(*buf));
|
2006-05-21 20:30:15 +04:00
|
|
|
*buf = le32_to_cpu(*buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Put an array of dwords in to main memory */
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int put_dwords(OHCIState *ohci,
|
|
|
|
uint32_t addr, uint32_t *buf, int num)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
addr += ohci->localmem_base;
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
|
|
|
uint32_t tmp = cpu_to_le32(*buf);
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
/* Get an array of words from main memory */
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int get_words(OHCIState *ohci,
|
|
|
|
uint32_t addr, uint16_t *buf, int num)
|
2007-10-31 03:34:21 +03:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
addr += ohci->localmem_base;
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_read(addr, buf, sizeof(*buf));
|
2007-10-31 03:34:21 +03:00
|
|
|
*buf = le16_to_cpu(*buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Put an array of words in to main memory */
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int put_words(OHCIState *ohci,
|
|
|
|
uint32_t addr, uint16_t *buf, int num)
|
2007-10-31 03:34:21 +03:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
addr += ohci->localmem_base;
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
|
|
|
uint16_t tmp = cpu_to_le16(*buf);
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
|
2007-10-31 03:34:21 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_read_ed(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_ed *ed)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2009-04-19 13:15:50 +04:00
|
|
|
return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_read_td(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_td *td)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2009-04-19 13:15:50 +04:00
|
|
|
return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_read_iso_td(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_iso_td *td)
|
2007-10-31 03:34:21 +03:00
|
|
|
{
|
2009-04-19 13:15:50 +04:00
|
|
|
return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
|
|
|
|
get_words(ohci, addr + 16, td->offset, 8));
|
2007-10-31 03:34:21 +03:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_read_hcca(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_hcca *hcca)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
|
2009-04-19 13:15:50 +04:00
|
|
|
return 1;
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_put_ed(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_ed *ed)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2009-04-19 13:15:50 +04:00
|
|
|
return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
static inline int ohci_put_td(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_td *td)
|
2007-10-31 03:34:21 +03:00
|
|
|
{
|
2009-04-19 13:15:50 +04:00
|
|
|
return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int ohci_put_iso_td(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_iso_td *td)
|
|
|
|
{
|
|
|
|
return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
|
|
|
|
put_words(ohci, addr + 16, td->offset, 8));
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int ohci_put_hcca(OHCIState *ohci,
|
|
|
|
uint32_t addr, struct ohci_hcca *hcca)
|
|
|
|
{
|
2011-04-10 20:23:39 +04:00
|
|
|
cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
|
2009-04-19 13:15:50 +04:00
|
|
|
return 1;
|
2007-10-31 03:34:21 +03:00
|
|
|
}
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
/* Read/Write the contents of a TD from/to main memory. */
|
2009-04-19 13:15:50 +04:00
|
|
|
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
|
|
|
|
uint8_t *buf, int len, int write)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
uint32_t ptr;
|
|
|
|
uint32_t n;
|
|
|
|
|
|
|
|
ptr = td->cbp;
|
|
|
|
n = 0x1000 - (ptr & 0xfff);
|
|
|
|
if (n > len)
|
|
|
|
n = len;
|
2009-04-19 13:15:50 +04:00
|
|
|
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
|
2006-05-21 20:30:15 +04:00
|
|
|
if (n == len)
|
|
|
|
return;
|
|
|
|
ptr = td->be & ~0xfffu;
|
2006-05-26 03:37:07 +04:00
|
|
|
buf += n;
|
2009-04-19 13:15:50 +04:00
|
|
|
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
/* Read/Write the contents of an ISO TD from/to main memory. */
|
2009-04-19 13:15:50 +04:00
|
|
|
static void ohci_copy_iso_td(OHCIState *ohci,
|
|
|
|
uint32_t start_addr, uint32_t end_addr,
|
2007-10-31 03:34:21 +03:00
|
|
|
uint8_t *buf, int len, int write)
|
|
|
|
{
|
|
|
|
uint32_t ptr;
|
|
|
|
uint32_t n;
|
2006-08-12 05:04:27 +04:00
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
ptr = start_addr;
|
|
|
|
n = 0x1000 - (ptr & 0xfff);
|
|
|
|
if (n > len)
|
|
|
|
n = len;
|
2009-04-19 13:15:50 +04:00
|
|
|
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
|
2007-10-31 03:34:21 +03:00
|
|
|
if (n == len)
|
|
|
|
return;
|
|
|
|
ptr = end_addr & ~0xfffu;
|
|
|
|
buf += n;
|
2009-04-19 13:15:50 +04:00
|
|
|
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
|
2007-10-31 03:34:21 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ohci_process_lists(OHCIState *ohci, int completion);
|
|
|
|
|
2011-06-21 13:52:28 +04:00
|
|
|
static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
|
2006-08-12 05:04:27 +04:00
|
|
|
{
|
2010-12-15 13:47:19 +03:00
|
|
|
OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
|
2006-08-12 05:04:27 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("Async packet complete\n");
|
2006-08-12 05:04:27 +04:00
|
|
|
#endif
|
|
|
|
ohci->async_complete = 1;
|
2007-10-31 03:34:21 +03:00
|
|
|
ohci_process_lists(ohci, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
|
|
|
|
|
|
|
|
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
|
|
|
|
int completion)
|
|
|
|
{
|
|
|
|
int dir;
|
|
|
|
size_t len = 0;
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_ISOCH
|
2008-09-14 10:45:34 +04:00
|
|
|
const char *str = NULL;
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2007-10-31 03:34:21 +03:00
|
|
|
int pid;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
USBDevice *dev;
|
|
|
|
struct ohci_iso_td iso_td;
|
|
|
|
uint32_t addr;
|
|
|
|
uint16_t starting_frame;
|
|
|
|
int16_t relative_frame_number;
|
|
|
|
int frame_count;
|
|
|
|
uint32_t start_offset, next_offset, end_offset = 0;
|
|
|
|
uint32_t start_addr, end_addr;
|
|
|
|
|
|
|
|
addr = ed->head & OHCI_DPTR_MASK;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
|
2007-10-31 03:34:21 +03:00
|
|
|
printf("usb-ohci: ISO_TD read error at %x\n", addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
starting_frame = OHCI_BM(iso_td.flags, TD_SF);
|
|
|
|
frame_count = OHCI_BM(iso_td.flags, TD_FC);
|
|
|
|
relative_frame_number = USUB(ohci->frame_number, starting_frame);
|
|
|
|
|
|
|
|
#ifdef DEBUG_ISOCH
|
|
|
|
printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
|
|
|
|
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
|
|
|
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
|
|
|
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
|
|
|
"frame_number 0x%.8x starting_frame 0x%.8x\n"
|
|
|
|
"frame_count 0x%.8x relative %d\n"
|
|
|
|
"di 0x%.8x cc 0x%.8x\n",
|
|
|
|
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
|
|
|
|
iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
|
|
|
|
iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
|
|
|
|
iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
|
|
|
|
ohci->frame_number, starting_frame,
|
|
|
|
frame_count, relative_frame_number,
|
|
|
|
OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (relative_frame_number < 0) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
|
2007-10-31 03:34:21 +03:00
|
|
|
return 1;
|
|
|
|
} else if (relative_frame_number > frame_count) {
|
|
|
|
/* ISO TD expired - retire the TD to the Done Queue and continue with
|
|
|
|
the next ISO TD of the same ED */
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
|
2007-10-31 03:34:21 +03:00
|
|
|
frame_count);
|
|
|
|
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
|
|
|
|
ed->head &= ~OHCI_DPTR_MASK;
|
|
|
|
ed->head |= (iso_td.next & OHCI_DPTR_MASK);
|
|
|
|
iso_td.next = ohci->done;
|
|
|
|
ohci->done = addr;
|
|
|
|
i = OHCI_BM(iso_td.flags, TD_DI);
|
|
|
|
if (i < ohci->done_count)
|
|
|
|
ohci->done_count = i;
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_put_iso_td(ohci, addr, &iso_td);
|
2007-10-31 03:34:21 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dir = OHCI_BM(ed->flags, ED_D);
|
|
|
|
switch (dir) {
|
|
|
|
case OHCI_TD_DIR_IN:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_ISOCH
|
2007-10-31 03:34:21 +03:00
|
|
|
str = "in";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2007-10-31 03:34:21 +03:00
|
|
|
pid = USB_TOKEN_IN;
|
|
|
|
break;
|
|
|
|
case OHCI_TD_DIR_OUT:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_ISOCH
|
2007-10-31 03:34:21 +03:00
|
|
|
str = "out";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2007-10-31 03:34:21 +03:00
|
|
|
pid = USB_TOKEN_OUT;
|
|
|
|
break;
|
|
|
|
case OHCI_TD_DIR_SETUP:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_ISOCH
|
2007-10-31 03:34:21 +03:00
|
|
|
str = "setup";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2007-10-31 03:34:21 +03:00
|
|
|
pid = USB_TOKEN_SETUP;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("usb-ohci: Bad direction %d\n", dir);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!iso_td.bp || !iso_td.be) {
|
|
|
|
printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
start_offset = iso_td.offset[relative_frame_number];
|
|
|
|
next_offset = iso_td.offset[relative_frame_number + 1];
|
|
|
|
|
|
|
|
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
|
|
|
|
((relative_frame_number < frame_count) &&
|
|
|
|
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
|
|
|
|
printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
|
|
|
|
start_offset, next_offset);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
|
|
|
|
printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
|
|
|
|
start_offset, next_offset);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((start_offset & 0x1000) == 0) {
|
|
|
|
start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
|
|
|
|
(start_offset & OHCI_OFFSET_MASK);
|
|
|
|
} else {
|
|
|
|
start_addr = (iso_td.be & OHCI_PAGE_MASK) |
|
|
|
|
(start_offset & OHCI_OFFSET_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (relative_frame_number < frame_count) {
|
|
|
|
end_offset = next_offset - 1;
|
|
|
|
if ((end_offset & 0x1000) == 0) {
|
|
|
|
end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
|
|
|
|
(end_offset & OHCI_OFFSET_MASK);
|
|
|
|
} else {
|
|
|
|
end_addr = (iso_td.be & OHCI_PAGE_MASK) |
|
|
|
|
(end_offset & OHCI_OFFSET_MASK);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Last packet in the ISO TD */
|
|
|
|
end_addr = iso_td.be;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
|
|
|
|
len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
|
|
|
|
- (start_addr & OHCI_OFFSET_MASK);
|
|
|
|
} else {
|
|
|
|
len = end_addr - start_addr + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (len && dir != OHCI_TD_DIR_IN) {
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
|
2007-10-31 03:34:21 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (completion) {
|
2011-07-12 17:22:25 +04:00
|
|
|
ret = ohci->usb_packet.result;
|
2007-10-31 03:34:21 +03:00
|
|
|
} else {
|
|
|
|
ret = USB_RET_NODEV;
|
|
|
|
for (i = 0; i < ohci->num_ports; i++) {
|
|
|
|
dev = ohci->rhport[i].port.dev;
|
|
|
|
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
|
|
|
|
continue;
|
2011-07-12 17:22:25 +04:00
|
|
|
usb_packet_setup(&ohci->usb_packet, pid,
|
|
|
|
OHCI_BM(ed->flags, ED_FA),
|
|
|
|
OHCI_BM(ed->flags, ED_EN));
|
|
|
|
usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len);
|
2011-05-12 15:20:39 +04:00
|
|
|
ret = usb_handle_packet(dev, &ohci->usb_packet);
|
2007-10-31 03:34:21 +03:00
|
|
|
if (ret != USB_RET_NODEV)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ret == USB_RET_ASYNC) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG_ISOCH
|
|
|
|
printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
|
|
|
|
start_offset, end_offset, start_addr, end_addr, str, len, ret);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Writeback */
|
|
|
|
if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
|
|
|
|
/* IN transfer succeeded */
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
|
2007-10-31 03:34:21 +03:00
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_NOERROR);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
|
|
|
|
} else if (dir == OHCI_TD_DIR_OUT && ret == len) {
|
|
|
|
/* OUT transfer succeeded */
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_NOERROR);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
|
|
|
|
} else {
|
2007-11-14 01:52:54 +03:00
|
|
|
if (ret > (ssize_t) len) {
|
2007-10-31 03:34:21 +03:00
|
|
|
printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_DATAOVERRUN);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
|
|
|
|
len);
|
|
|
|
} else if (ret >= 0) {
|
|
|
|
printf("usb-ohci: DataUnderrun %d\n", ret);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_DATAUNDERRUN);
|
|
|
|
} else {
|
|
|
|
switch (ret) {
|
|
|
|
case USB_RET_NODEV:
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_DEVICENOTRESPONDING);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
|
|
|
|
0);
|
|
|
|
break;
|
|
|
|
case USB_RET_NAK:
|
|
|
|
case USB_RET_STALL:
|
|
|
|
printf("usb-ohci: got NAK/STALL %d\n", ret);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_STALL);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
|
|
|
|
0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("usb-ohci: Bad device response %d\n", ret);
|
|
|
|
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
|
|
|
|
OHCI_CC_UNDEXPETEDPID);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (relative_frame_number == frame_count) {
|
|
|
|
/* Last data packet of ISO TD - retire the TD to the Done Queue */
|
|
|
|
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
|
|
|
|
ed->head &= ~OHCI_DPTR_MASK;
|
|
|
|
ed->head |= (iso_td.next & OHCI_DPTR_MASK);
|
|
|
|
iso_td.next = ohci->done;
|
|
|
|
ohci->done = addr;
|
|
|
|
i = OHCI_BM(iso_td.flags, TD_DI);
|
|
|
|
if (i < ohci->done_count)
|
|
|
|
ohci->done_count = i;
|
|
|
|
}
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_put_iso_td(ohci, addr, &iso_td);
|
2007-10-31 03:34:21 +03:00
|
|
|
return 1;
|
2006-08-12 05:04:27 +04:00
|
|
|
}
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
/* Service a transport descriptor.
|
|
|
|
Returns nonzero to terminate processing of this endpoint. */
|
|
|
|
|
|
|
|
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
|
|
|
|
{
|
|
|
|
int dir;
|
|
|
|
size_t len = 0;
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2008-09-14 10:45:34 +04:00
|
|
|
const char *str = NULL;
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2006-05-21 20:30:15 +04:00
|
|
|
int pid;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
USBDevice *dev;
|
|
|
|
struct ohci_td td;
|
|
|
|
uint32_t addr;
|
|
|
|
int flag_r;
|
2006-08-12 05:04:27 +04:00
|
|
|
int completion;
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
addr = ed->head & OHCI_DPTR_MASK;
|
2006-08-12 05:04:27 +04:00
|
|
|
/* See if this TD has already been submitted to the device. */
|
|
|
|
completion = (addr == ohci->async_td);
|
|
|
|
if (completion && !ohci->async_complete) {
|
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("Skipping async TD\n");
|
2006-08-12 05:04:27 +04:00
|
|
|
#endif
|
|
|
|
return 1;
|
|
|
|
}
|
2009-04-19 13:15:50 +04:00
|
|
|
if (!ohci_read_td(ohci, addr, &td)) {
|
2006-05-21 20:30:15 +04:00
|
|
|
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dir = OHCI_BM(ed->flags, ED_D);
|
|
|
|
switch (dir) {
|
|
|
|
case OHCI_TD_DIR_OUT:
|
|
|
|
case OHCI_TD_DIR_IN:
|
|
|
|
/* Same value. */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dir = OHCI_BM(td.flags, TD_DP);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (dir) {
|
|
|
|
case OHCI_TD_DIR_IN:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2006-05-21 20:30:15 +04:00
|
|
|
str = "in";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2006-05-21 20:30:15 +04:00
|
|
|
pid = USB_TOKEN_IN;
|
|
|
|
break;
|
|
|
|
case OHCI_TD_DIR_OUT:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2006-05-21 20:30:15 +04:00
|
|
|
str = "out";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2006-05-21 20:30:15 +04:00
|
|
|
pid = USB_TOKEN_OUT;
|
|
|
|
break;
|
|
|
|
case OHCI_TD_DIR_SETUP:
|
2010-04-25 22:23:04 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2006-05-21 20:30:15 +04:00
|
|
|
str = "setup";
|
2010-04-25 22:23:04 +04:00
|
|
|
#endif
|
2006-05-21 20:30:15 +04:00
|
|
|
pid = USB_TOKEN_SETUP;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "usb-ohci: Bad direction\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
if (td.cbp && td.be) {
|
2006-05-26 03:37:07 +04:00
|
|
|
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
|
|
|
|
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
|
|
|
|
} else {
|
|
|
|
len = (td.be - td.cbp) + 1;
|
|
|
|
}
|
|
|
|
|
2006-08-12 05:04:27 +04:00
|
|
|
if (len && dir != OHCI_TD_DIR_IN && !completion) {
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
flag_r = (td.flags & OHCI_TD_R) != 0;
|
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
|
2010-03-14 14:19:03 +03:00
|
|
|
addr, (int64_t)len, str, flag_r, td.cbp, td.be);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2007-11-14 01:52:54 +03:00
|
|
|
if (len > 0 && dir != OHCI_TD_DIR_IN) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF(" data:");
|
2006-05-21 20:30:15 +04:00
|
|
|
for (i = 0; i < len; i++)
|
2006-08-12 05:04:27 +04:00
|
|
|
printf(" %.2x", ohci->usb_buf[i]);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
#endif
|
2006-08-12 05:04:27 +04:00
|
|
|
if (completion) {
|
2011-07-12 17:22:25 +04:00
|
|
|
ret = ohci->usb_packet.result;
|
2006-08-12 05:04:27 +04:00
|
|
|
ohci->async_td = 0;
|
|
|
|
ohci->async_complete = 0;
|
|
|
|
} else {
|
|
|
|
ret = USB_RET_NODEV;
|
|
|
|
for (i = 0; i < ohci->num_ports; i++) {
|
|
|
|
dev = ohci->rhport[i].port.dev;
|
|
|
|
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (ohci->async_td) {
|
|
|
|
/* ??? The hardware should allow one active packet per
|
|
|
|
endpoint. We only allow one active packet per controller.
|
|
|
|
This should be sufficient as long as devices respond in a
|
|
|
|
timely manner.
|
|
|
|
*/
|
2006-05-21 20:30:15 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("Too many pending packets\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
#endif
|
2006-08-12 05:04:27 +04:00
|
|
|
return 1;
|
|
|
|
}
|
2011-07-12 17:22:25 +04:00
|
|
|
usb_packet_setup(&ohci->usb_packet, pid,
|
|
|
|
OHCI_BM(ed->flags, ED_FA),
|
|
|
|
OHCI_BM(ed->flags, ED_EN));
|
|
|
|
usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len);
|
2011-05-12 15:20:39 +04:00
|
|
|
ret = usb_handle_packet(dev, &ohci->usb_packet);
|
2006-08-12 05:04:27 +04:00
|
|
|
if (ret != USB_RET_NODEV)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("ret=%d\n", ret);
|
2006-08-12 05:04:27 +04:00
|
|
|
#endif
|
|
|
|
if (ret == USB_RET_ASYNC) {
|
|
|
|
ohci->async_td = addr;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
if (ret >= 0) {
|
|
|
|
if (dir == OHCI_TD_DIR_IN) {
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
|
2006-05-21 20:30:15 +04:00
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF(" data:");
|
2006-05-21 20:30:15 +04:00
|
|
|
for (i = 0; i < ret; i++)
|
2006-08-12 05:04:27 +04:00
|
|
|
printf(" %.2x", ohci->usb_buf[i]);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
ret = len;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Writeback */
|
|
|
|
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
|
|
|
|
/* Transmission succeeded. */
|
|
|
|
if (ret == len) {
|
|
|
|
td.cbp = 0;
|
|
|
|
} else {
|
|
|
|
td.cbp += ret;
|
|
|
|
if ((td.cbp & 0xfff) + ret > 0xfff) {
|
|
|
|
td.cbp &= 0xfff;
|
|
|
|
td.cbp |= td.be & ~0xfff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
td.flags |= OHCI_TD_T1;
|
|
|
|
td.flags ^= OHCI_TD_T0;
|
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
|
|
|
|
OHCI_SET_BM(td.flags, TD_EC, 0);
|
|
|
|
|
|
|
|
ed->head &= ~OHCI_ED_C;
|
|
|
|
if (td.flags & OHCI_TD_T0)
|
|
|
|
ed->head |= OHCI_ED_C;
|
|
|
|
} else {
|
|
|
|
if (ret >= 0) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: Underrun\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
|
|
|
|
} else {
|
|
|
|
switch (ret) {
|
|
|
|
case USB_RET_NODEV:
|
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
|
|
|
|
case USB_RET_NAK:
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: got NAK\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
return 1;
|
|
|
|
case USB_RET_STALL:
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: got STALL\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
|
|
|
|
break;
|
|
|
|
case USB_RET_BABBLE:
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: got BABBLE\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
|
|
|
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
|
|
|
|
OHCI_SET_BM(td.flags, TD_EC, 3);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ed->head |= OHCI_ED_H;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Retire this TD */
|
|
|
|
ed->head &= ~OHCI_DPTR_MASK;
|
|
|
|
ed->head |= td.next & OHCI_DPTR_MASK;
|
|
|
|
td.next = ohci->done;
|
|
|
|
ohci->done = addr;
|
|
|
|
i = OHCI_BM(td.flags, TD_DI);
|
|
|
|
if (i < ohci->done_count)
|
|
|
|
ohci->done_count = i;
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_put_td(ohci, addr, &td);
|
2006-05-21 20:30:15 +04:00
|
|
|
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
2007-10-31 03:34:21 +03:00
|
|
|
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
struct ohci_ed ed;
|
|
|
|
uint32_t next_ed;
|
|
|
|
uint32_t cur;
|
|
|
|
int active;
|
|
|
|
|
|
|
|
active = 0;
|
|
|
|
|
|
|
|
if (head == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (cur = head; cur; cur = next_ed) {
|
2009-04-19 13:15:50 +04:00
|
|
|
if (!ohci_read_ed(ohci, cur, &ed)) {
|
2006-05-21 20:30:15 +04:00
|
|
|
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
next_ed = ed.next & OHCI_DPTR_MASK;
|
|
|
|
|
2006-08-12 05:04:27 +04:00
|
|
|
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
|
|
|
|
uint32_t addr;
|
|
|
|
/* Cancel pending packets for ED that have been paused. */
|
|
|
|
addr = ed.head & OHCI_DPTR_MASK;
|
|
|
|
if (ohci->async_td && addr == ohci->async_td) {
|
|
|
|
usb_cancel_packet(&ohci->usb_packet);
|
|
|
|
ohci->async_td = 0;
|
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
continue;
|
2006-08-12 05:04:27 +04:00
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
|
|
|
#ifdef DEBUG_PACKET
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
2006-05-21 20:30:15 +04:00
|
|
|
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
|
|
|
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
|
|
|
|
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
|
|
|
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
|
|
|
|
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
|
|
|
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
|
|
|
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
|
|
|
|
#endif
|
|
|
|
active = 1;
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
if ((ed.flags & OHCI_ED_F) == 0) {
|
|
|
|
if (ohci_service_td(ohci, &ed))
|
|
|
|
break;
|
|
|
|
} else {
|
|
|
|
/* Handle isochronous endpoints */
|
|
|
|
if (ohci_service_iso_td(ohci, &ed, completion))
|
|
|
|
break;
|
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_put_ed(ohci, cur, &ed);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
return active;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generate a SOF event, and set a timer for EOF */
|
|
|
|
static void ohci_sof(OHCIState *ohci)
|
|
|
|
{
|
2011-03-11 18:47:48 +03:00
|
|
|
ohci->sof_time = qemu_get_clock_ns(vm_clock);
|
2006-05-21 20:30:15 +04:00
|
|
|
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
|
|
|
|
ohci_set_interrupt(ohci, OHCI_INTR_SF);
|
|
|
|
}
|
|
|
|
|
2006-08-12 05:04:27 +04:00
|
|
|
/* Process Control and Bulk lists. */
|
2007-10-31 03:34:21 +03:00
|
|
|
static void ohci_process_lists(OHCIState *ohci, int completion)
|
2006-08-12 05:04:27 +04:00
|
|
|
{
|
|
|
|
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
2010-04-18 18:22:14 +04:00
|
|
|
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
|
|
|
|
DPRINTF("usb-ohci: head %x, cur %x\n",
|
|
|
|
ohci->ctrl_head, ohci->ctrl_cur);
|
|
|
|
}
|
2007-10-31 03:34:21 +03:00
|
|
|
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
|
2006-08-12 05:04:27 +04:00
|
|
|
ohci->ctrl_cur = 0;
|
|
|
|
ohci->status &= ~OHCI_STATUS_CLF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
2007-10-31 03:34:21 +03:00
|
|
|
if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
|
2006-08-12 05:04:27 +04:00
|
|
|
ohci->bulk_cur = 0;
|
|
|
|
ohci->status &= ~OHCI_STATUS_BLF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
/* Do frame processing on frame boundary */
|
|
|
|
static void ohci_frame_boundary(void *opaque)
|
|
|
|
{
|
|
|
|
OHCIState *ohci = opaque;
|
|
|
|
struct ohci_hcca hcca;
|
|
|
|
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_read_hcca(ohci, ohci->hcca, &hcca);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
/* Process all the lists at the end of the frame */
|
|
|
|
if (ohci->ctl & OHCI_CTL_PLE) {
|
|
|
|
int n;
|
|
|
|
|
|
|
|
n = ohci->frame_number & 0x1f;
|
2007-10-31 03:34:21 +03:00
|
|
|
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2006-08-12 05:04:27 +04:00
|
|
|
/* Cancel all pending packets if either of the lists has been disabled. */
|
|
|
|
if (ohci->async_td &&
|
|
|
|
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
|
|
|
|
usb_cancel_packet(&ohci->usb_packet);
|
|
|
|
ohci->async_td = 0;
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
2006-08-12 05:04:27 +04:00
|
|
|
ohci->old_ctl = ohci->ctl;
|
2007-10-31 03:34:21 +03:00
|
|
|
ohci_process_lists(ohci, 0);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
/* Frame boundary, so do EOF stuf here */
|
|
|
|
ohci->frt = ohci->fit;
|
|
|
|
|
2009-07-08 23:54:28 +04:00
|
|
|
/* Increment frame number and take care of endianness. */
|
2006-05-21 20:30:15 +04:00
|
|
|
ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
|
2009-07-08 23:54:28 +04:00
|
|
|
hcca.frame = cpu_to_le16(ohci->frame_number);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
|
|
|
|
if (!ohci->done)
|
|
|
|
abort();
|
|
|
|
if (ohci->intr & ohci->intr_status)
|
|
|
|
ohci->done |= 1;
|
|
|
|
hcca.done = cpu_to_le32(ohci->done);
|
|
|
|
ohci->done = 0;
|
|
|
|
ohci->done_count = 7;
|
|
|
|
ohci_set_interrupt(ohci, OHCI_INTR_WD);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ohci->done_count != 7 && ohci->done_count != 0)
|
|
|
|
ohci->done_count--;
|
|
|
|
|
|
|
|
/* Do SOF stuff here */
|
|
|
|
ohci_sof(ohci);
|
|
|
|
|
|
|
|
/* Writeback HCCA */
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci_put_hcca(ohci, ohci->hcca, &hcca);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Start sending SOF tokens across the USB bus, lists are processed in
|
|
|
|
* next frame
|
|
|
|
*/
|
|
|
|
static int ohci_bus_start(OHCIState *ohci)
|
|
|
|
{
|
2011-03-11 18:47:48 +03:00
|
|
|
ohci->eof_timer = qemu_new_timer_ns(vm_clock,
|
2006-05-21 20:30:15 +04:00
|
|
|
ohci_frame_boundary,
|
|
|
|
ohci);
|
|
|
|
|
|
|
|
if (ohci->eof_timer == NULL) {
|
2011-03-11 18:47:48 +03:00
|
|
|
fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
/* TODO: Signal unrecoverable error */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
ohci_sof(ohci);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Stop sending SOF tokens on the bus */
|
|
|
|
static void ohci_bus_stop(OHCIState *ohci)
|
|
|
|
{
|
|
|
|
if (ohci->eof_timer)
|
|
|
|
qemu_del_timer(ohci->eof_timer);
|
2007-07-25 20:50:37 +04:00
|
|
|
ohci->eof_timer = NULL;
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Sets a flag in a port status register but only set it if the port is
|
|
|
|
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
|
|
|
* return 1.
|
|
|
|
*/
|
|
|
|
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
|
|
|
|
{
|
|
|
|
int ret = 1;
|
|
|
|
|
|
|
|
/* writing a 0 has no effect */
|
|
|
|
if (val == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* If CurrentConnectStatus is cleared we set
|
|
|
|
* ConnectStatusChange
|
|
|
|
*/
|
|
|
|
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
|
|
|
ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
|
|
|
|
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
|
|
|
/* TODO: CSC is a wakeup event */
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ohci->rhport[i].ctrl & val)
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
/* set the bit */
|
|
|
|
ohci->rhport[i].ctrl |= val;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
|
|
|
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
|
|
|
|
{
|
|
|
|
val &= OHCI_FMI_FI;
|
|
|
|
|
|
|
|
if (val != ohci->fi) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
2007-03-17 19:59:31 +03:00
|
|
|
ohci->name, ohci->fi, ohci->fi);
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
ohci->fi = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ohci_port_power(OHCIState *ohci, int i, int p)
|
|
|
|
{
|
|
|
|
if (p) {
|
|
|
|
ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
|
|
|
|
} else {
|
|
|
|
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
|
|
|
|
OHCI_PORT_CCS|
|
|
|
|
OHCI_PORT_PSS|
|
|
|
|
OHCI_PORT_PRS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set HcControlRegister */
|
|
|
|
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t old_state;
|
|
|
|
uint32_t new_state;
|
|
|
|
|
|
|
|
old_state = ohci->ctl & OHCI_CTL_HCFS;
|
|
|
|
ohci->ctl = val;
|
|
|
|
new_state = ohci->ctl & OHCI_CTL_HCFS;
|
|
|
|
|
|
|
|
/* no state change */
|
|
|
|
if (old_state == new_state)
|
|
|
|
return;
|
|
|
|
|
|
|
|
switch (new_state) {
|
|
|
|
case OHCI_USB_OPERATIONAL:
|
|
|
|
ohci_bus_start(ohci);
|
|
|
|
break;
|
|
|
|
case OHCI_USB_SUSPEND:
|
|
|
|
ohci_bus_stop(ohci);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
break;
|
|
|
|
case OHCI_USB_RESUME:
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
break;
|
|
|
|
case OHCI_USB_RESET:
|
2007-07-25 20:50:37 +04:00
|
|
|
ohci_reset(ohci);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
|
2006-05-21 20:30:15 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
|
|
|
{
|
|
|
|
uint16_t fr;
|
|
|
|
int64_t tks;
|
|
|
|
|
|
|
|
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
|
|
|
return (ohci->frt << 31);
|
|
|
|
|
|
|
|
/* Being in USB operational state guarnatees sof_time was
|
|
|
|
* set already.
|
|
|
|
*/
|
2011-03-11 18:47:48 +03:00
|
|
|
tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
/* avoid muldiv if possible */
|
|
|
|
if (tks >= usb_frame_time)
|
|
|
|
return (ohci->frt << 31);
|
|
|
|
|
|
|
|
tks = muldiv64(1, tks, usb_bit_time);
|
|
|
|
fr = (uint16_t)(ohci->fi - tks);
|
|
|
|
|
|
|
|
return (ohci->frt << 31) | fr;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Set root hub status */
|
|
|
|
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t old_state;
|
|
|
|
|
|
|
|
old_state = ohci->rhstatus;
|
|
|
|
|
|
|
|
/* write 1 to clear OCIC */
|
|
|
|
if (val & OHCI_RHS_OCIC)
|
|
|
|
ohci->rhstatus &= ~OHCI_RHS_OCIC;
|
|
|
|
|
|
|
|
if (val & OHCI_RHS_LPS) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ohci->num_ports; i++)
|
|
|
|
ohci_port_power(ohci, i, 0);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: powered down all ports\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (val & OHCI_RHS_LPSC) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ohci->num_ports; i++)
|
|
|
|
ohci_port_power(ohci, i, 1);
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: powered up all ports\n");
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (val & OHCI_RHS_DRWE)
|
|
|
|
ohci->rhstatus |= OHCI_RHS_DRWE;
|
|
|
|
|
|
|
|
if (val & OHCI_RHS_CRWE)
|
|
|
|
ohci->rhstatus &= ~OHCI_RHS_DRWE;
|
|
|
|
|
|
|
|
if (old_state != ohci->rhstatus)
|
|
|
|
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set root hub port status */
|
|
|
|
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t old_state;
|
|
|
|
OHCIPort *port;
|
|
|
|
|
|
|
|
port = &ohci->rhport[portnum];
|
|
|
|
old_state = port->ctrl;
|
|
|
|
|
|
|
|
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
|
|
|
if (val & OHCI_PORT_WTC)
|
|
|
|
port->ctrl &= ~(val & OHCI_PORT_WTC);
|
|
|
|
|
|
|
|
if (val & OHCI_PORT_CCS)
|
|
|
|
port->ctrl &= ~OHCI_PORT_PES;
|
|
|
|
|
|
|
|
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
|
|
|
|
|
2010-04-18 18:22:14 +04:00
|
|
|
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
|
2010-04-18 18:22:14 +04:00
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
|
2006-08-12 05:04:27 +04:00
|
|
|
usb_send_msg(port->port.dev, USB_MSG_RESET);
|
2006-05-21 20:30:15 +04:00
|
|
|
port->ctrl &= ~OHCI_PORT_PRS;
|
|
|
|
/* ??? Should this also set OHCI_PORT_PESC. */
|
|
|
|
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Invert order here to ensure in ambiguous case, device is
|
|
|
|
* powered up...
|
|
|
|
*/
|
|
|
|
if (val & OHCI_PORT_LSDA)
|
|
|
|
ohci_port_power(ohci, portnum, 0);
|
|
|
|
if (val & OHCI_PORT_PPS)
|
|
|
|
ohci_port_power(ohci, portnum, 1);
|
|
|
|
|
|
|
|
if (old_state != port->ctrl)
|
|
|
|
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-07-26 15:26:22 +04:00
|
|
|
static uint64_t ohci_mem_read(void *opaque,
|
|
|
|
target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2011-07-26 15:26:22 +04:00
|
|
|
OHCIState *ohci = opaque;
|
2009-01-18 23:56:30 +03:00
|
|
|
uint32_t retval;
|
2006-05-21 20:30:15 +04:00
|
|
|
|
|
|
|
/* Only aligned reads are allowed on OHCI */
|
|
|
|
if (addr & 3) {
|
|
|
|
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
|
|
|
return 0xffffffff;
|
2009-01-18 23:56:30 +03:00
|
|
|
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
|
2006-05-21 20:30:15 +04:00
|
|
|
/* HcRhPortStatus */
|
2009-01-18 23:56:30 +03:00
|
|
|
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
|
|
|
|
} else {
|
|
|
|
switch (addr >> 2) {
|
|
|
|
case 0: /* HcRevision */
|
|
|
|
retval = 0x10;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 1: /* HcControl */
|
|
|
|
retval = ohci->ctl;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 2: /* HcCommandStatus */
|
|
|
|
retval = ohci->status;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 3: /* HcInterruptStatus */
|
|
|
|
retval = ohci->intr_status;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 4: /* HcInterruptEnable */
|
|
|
|
case 5: /* HcInterruptDisable */
|
|
|
|
retval = ohci->intr;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 6: /* HcHCCA */
|
|
|
|
retval = ohci->hcca;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 7: /* HcPeriodCurrentED */
|
|
|
|
retval = ohci->per_cur;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 8: /* HcControlHeadED */
|
|
|
|
retval = ohci->ctrl_head;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 9: /* HcControlCurrentED */
|
|
|
|
retval = ohci->ctrl_cur;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 10: /* HcBulkHeadED */
|
|
|
|
retval = ohci->bulk_head;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 11: /* HcBulkCurrentED */
|
|
|
|
retval = ohci->bulk_cur;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 12: /* HcDoneHead */
|
|
|
|
retval = ohci->done;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 13: /* HcFmInterretval */
|
|
|
|
retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 14: /* HcFmRemaining */
|
|
|
|
retval = ohci_get_frame_remaining(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 15: /* HcFmNumber */
|
|
|
|
retval = ohci->frame_number;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 16: /* HcPeriodicStart */
|
|
|
|
retval = ohci->pstart;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 17: /* HcLSThreshold */
|
|
|
|
retval = ohci->lst;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 18: /* HcRhDescriptorA */
|
|
|
|
retval = ohci->rhdesc_a;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 19: /* HcRhDescriptorB */
|
|
|
|
retval = ohci->rhdesc_b;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 20: /* HcRhStatus */
|
|
|
|
retval = ohci->rhstatus;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* PXA27x specific registers */
|
|
|
|
case 24: /* HcStatus */
|
|
|
|
retval = ohci->hstatus & ohci->hmask;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 25: /* HcHReset */
|
|
|
|
retval = ohci->hreset;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 26: /* HcHInterruptEnable */
|
|
|
|
retval = ohci->hmask;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 27: /* HcHInterruptTest */
|
|
|
|
retval = ohci->htest;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
|
|
|
|
retval = 0xffffffff;
|
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2009-01-18 23:56:30 +03:00
|
|
|
return retval;
|
2006-05-21 20:30:15 +04:00
|
|
|
}
|
|
|
|
|
2011-07-26 15:26:22 +04:00
|
|
|
static void ohci_mem_write(void *opaque,
|
|
|
|
target_phys_addr_t addr,
|
|
|
|
uint64_t val,
|
|
|
|
unsigned size)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
2011-07-26 15:26:22 +04:00
|
|
|
OHCIState *ohci = opaque;
|
2010-06-14 02:37:31 +04:00
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
/* Only aligned reads are allowed on OHCI */
|
|
|
|
if (addr & 3) {
|
|
|
|
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
|
|
|
|
/* HcRhPortStatus */
|
|
|
|
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (addr >> 2) {
|
|
|
|
case 1: /* HcControl */
|
|
|
|
ohci_set_ctl(ohci, val);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 2: /* HcCommandStatus */
|
|
|
|
/* SOC is read-only */
|
|
|
|
val = (val & ~OHCI_STATUS_SOC);
|
|
|
|
|
|
|
|
/* Bits written as '0' remain unchanged in the register */
|
|
|
|
ohci->status |= val;
|
|
|
|
|
|
|
|
if (ohci->status & OHCI_STATUS_HCR)
|
|
|
|
ohci_reset(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 3: /* HcInterruptStatus */
|
|
|
|
ohci->intr_status &= ~val;
|
|
|
|
ohci_intr_update(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 4: /* HcInterruptEnable */
|
|
|
|
ohci->intr |= val;
|
|
|
|
ohci_intr_update(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 5: /* HcInterruptDisable */
|
|
|
|
ohci->intr &= ~val;
|
|
|
|
ohci_intr_update(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 6: /* HcHCCA */
|
|
|
|
ohci->hcca = val & OHCI_HCCA_MASK;
|
|
|
|
break;
|
|
|
|
|
2011-06-07 23:02:29 +04:00
|
|
|
case 7: /* HcPeriodCurrentED */
|
|
|
|
/* Ignore writes to this read-only register, Linux does them */
|
|
|
|
break;
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
case 8: /* HcControlHeadED */
|
|
|
|
ohci->ctrl_head = val & OHCI_EDPTR_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 9: /* HcControlCurrentED */
|
|
|
|
ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 10: /* HcBulkHeadED */
|
|
|
|
ohci->bulk_head = val & OHCI_EDPTR_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 11: /* HcBulkCurrentED */
|
|
|
|
ohci->bulk_cur = val & OHCI_EDPTR_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 13: /* HcFmInterval */
|
|
|
|
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
|
|
|
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
|
|
|
ohci_set_frame_interval(ohci, val);
|
|
|
|
break;
|
|
|
|
|
2007-10-31 03:34:21 +03:00
|
|
|
case 15: /* HcFmNumber */
|
|
|
|
break;
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
case 16: /* HcPeriodicStart */
|
|
|
|
ohci->pstart = val & 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 17: /* HcLSThreshold */
|
|
|
|
ohci->lst = val & 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 18: /* HcRhDescriptorA */
|
|
|
|
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
|
|
|
|
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 19: /* HcRhDescriptorB */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 20: /* HcRhStatus */
|
|
|
|
ohci_set_hub_status(ohci, val);
|
|
|
|
break;
|
|
|
|
|
2007-03-17 19:59:31 +03:00
|
|
|
/* PXA27x specific registers */
|
|
|
|
case 24: /* HcStatus */
|
|
|
|
ohci->hstatus &= ~(val & ohci->hmask);
|
|
|
|
|
|
|
|
case 25: /* HcHReset */
|
|
|
|
ohci->hreset = val & ~OHCI_HRESET_FSBIR;
|
|
|
|
if (val & OHCI_HRESET_FSBIR)
|
|
|
|
ohci_reset(ohci);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 26: /* HcHInterruptEnable */
|
|
|
|
ohci->hmask = val;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 27: /* HcHInterruptTest */
|
|
|
|
ohci->htest = val;
|
|
|
|
break;
|
|
|
|
|
2006-05-21 20:30:15 +04:00
|
|
|
default:
|
|
|
|
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-24 14:31:11 +04:00
|
|
|
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
|
2011-05-23 19:37:12 +04:00
|
|
|
{
|
|
|
|
if (ohci->async_td && ohci->usb_packet.owner == dev) {
|
|
|
|
usb_cancel_packet(&ohci->usb_packet);
|
|
|
|
ohci->async_td = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-26 15:26:22 +04:00
|
|
|
static const MemoryRegionOps ohci_mem_ops = {
|
|
|
|
.read = ohci_mem_read,
|
|
|
|
.write = ohci_mem_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2006-05-21 20:30:15 +04:00
|
|
|
};
|
|
|
|
|
2010-12-01 13:08:44 +03:00
|
|
|
static USBPortOps ohci_port_ops = {
|
|
|
|
.attach = ohci_attach,
|
2010-12-01 13:27:05 +03:00
|
|
|
.detach = ohci_detach,
|
2011-06-24 14:31:11 +04:00
|
|
|
.child_detach = ohci_child_detach,
|
2011-06-07 22:50:12 +04:00
|
|
|
.wakeup = ohci_wakeup,
|
2010-12-16 19:03:44 +03:00
|
|
|
.complete = ohci_async_complete_packet,
|
2010-12-01 13:08:44 +03:00
|
|
|
};
|
|
|
|
|
2011-05-23 19:37:12 +04:00
|
|
|
static USBBusOps ohci_bus_ops = {
|
|
|
|
};
|
|
|
|
|
2011-06-24 22:29:05 +04:00
|
|
|
static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
|
|
|
|
int num_ports, uint32_t localmem_base,
|
|
|
|
char *masterbus, uint32_t firstport)
|
2006-05-21 20:30:15 +04:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (usb_frame_time == 0) {
|
2008-09-06 21:47:39 +04:00
|
|
|
#ifdef OHCI_TIME_WARP
|
2009-09-10 05:04:26 +04:00
|
|
|
usb_frame_time = get_ticks_per_sec();
|
|
|
|
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
|
2006-05-21 20:30:15 +04:00
|
|
|
#else
|
2009-09-10 05:04:26 +04:00
|
|
|
usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
|
|
|
|
if (get_ticks_per_sec() >= USB_HZ) {
|
|
|
|
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
|
2006-05-21 20:30:15 +04:00
|
|
|
} else {
|
|
|
|
usb_bit_time = 1;
|
|
|
|
}
|
|
|
|
#endif
|
2010-02-07 02:03:50 +03:00
|
|
|
DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
|
2006-05-21 20:30:15 +04:00
|
|
|
usb_frame_time, usb_bit_time);
|
|
|
|
}
|
|
|
|
|
2011-06-24 22:29:05 +04:00
|
|
|
ohci->num_ports = num_ports;
|
|
|
|
if (masterbus) {
|
|
|
|
USBPort *ports[OHCI_MAX_PORTS];
|
|
|
|
for(i = 0; i < num_ports; i++) {
|
|
|
|
ports[i] = &ohci->rhport[i].port;
|
|
|
|
}
|
|
|
|
if (usb_register_companion(masterbus, ports, num_ports,
|
|
|
|
firstport, ohci, &ohci_port_ops,
|
|
|
|
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
|
|
|
|
for (i = 0; i < num_ports; i++) {
|
|
|
|
usb_register_port(&ohci->bus, &ohci->rhport[i].port,
|
|
|
|
ohci, i, &ohci_port_ops,
|
|
|
|
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-26 15:26:22 +04:00
|
|
|
memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256);
|
2009-04-19 13:15:50 +04:00
|
|
|
ohci->localmem_base = localmem_base;
|
2007-03-17 19:59:31 +03:00
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
ohci->name = dev->info->name;
|
2011-07-12 17:22:25 +04:00
|
|
|
usb_packet_init(&ohci->usb_packet);
|
2007-03-17 19:59:31 +03:00
|
|
|
|
|
|
|
ohci->async_td = 0;
|
2009-06-27 11:25:07 +04:00
|
|
|
qemu_register_reset(ohci_reset, ohci);
|
2011-06-24 22:29:05 +04:00
|
|
|
|
|
|
|
return 0;
|
2007-03-17 19:59:31 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
typedef struct {
|
|
|
|
PCIDevice pci_dev;
|
|
|
|
OHCIState state;
|
2011-06-24 22:29:05 +04:00
|
|
|
char *masterbus;
|
|
|
|
uint32_t num_ports;
|
|
|
|
uint32_t firstport;
|
2007-03-17 19:59:31 +03:00
|
|
|
} OHCIPCIState;
|
|
|
|
|
2009-08-31 16:24:03 +04:00
|
|
|
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
|
2007-03-17 19:59:31 +03:00
|
|
|
{
|
2009-08-31 16:24:03 +04:00
|
|
|
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2009-12-10 20:27:32 +03:00
|
|
|
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
|
2011-09-11 14:40:23 +04:00
|
|
|
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2011-06-24 22:29:05 +04:00
|
|
|
if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
|
|
|
|
ohci->masterbus, ohci->firstport) != 0) {
|
|
|
|
return -1;
|
|
|
|
}
|
2010-04-05 22:57:40 +04:00
|
|
|
ohci->state.irq = ohci->pci_dev.irq[0];
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2009-12-10 20:27:32 +03:00
|
|
|
/* TODO: avoid cast below by using dev */
|
2011-08-08 17:09:31 +04:00
|
|
|
pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem);
|
2009-08-31 16:24:03 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-04-05 00:18:26 +04:00
|
|
|
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
|
2009-08-31 16:24:03 +04:00
|
|
|
{
|
2010-04-05 00:18:26 +04:00
|
|
|
pci_create_simple(bus, devfn, "pci-ohci");
|
2007-03-17 19:59:31 +03:00
|
|
|
}
|
2006-05-21 20:30:15 +04:00
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
typedef struct {
|
|
|
|
SysBusDevice busdev;
|
|
|
|
OHCIState ohci;
|
|
|
|
uint32_t num_ports;
|
|
|
|
target_phys_addr_t dma_offset;
|
|
|
|
} OHCISysBusState;
|
2009-04-19 13:15:50 +04:00
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
static int ohci_init_pxa(SysBusDevice *dev)
|
2009-04-19 13:15:50 +04:00
|
|
|
{
|
2010-04-05 22:57:40 +04:00
|
|
|
OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
|
2009-04-19 13:15:50 +04:00
|
|
|
|
2011-06-24 22:29:05 +04:00
|
|
|
/* Cannot fail as we pass NULL for masterbus */
|
|
|
|
usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0);
|
2010-04-05 22:57:40 +04:00
|
|
|
sysbus_init_irq(dev, &s->ohci.irq);
|
2011-07-26 15:26:22 +04:00
|
|
|
sysbus_init_mmio_region(dev, &s->ohci.mem);
|
2009-04-19 13:15:50 +04:00
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
return 0;
|
2009-04-19 13:15:50 +04:00
|
|
|
}
|
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
static PCIDeviceInfo ohci_pci_info = {
|
2009-12-09 19:07:53 +03:00
|
|
|
.qdev.name = "pci-ohci",
|
2009-08-31 16:24:03 +04:00
|
|
|
.qdev.desc = "Apple USB Controller",
|
|
|
|
.qdev.size = sizeof(OHCIPCIState),
|
|
|
|
.init = usb_ohci_initfn_pci,
|
2011-05-25 05:58:29 +04:00
|
|
|
.vendor_id = PCI_VENDOR_ID_APPLE,
|
|
|
|
.device_id = PCI_DEVICE_ID_APPLE_IPID_USB,
|
|
|
|
.class_id = PCI_CLASS_SERIAL_USB,
|
2011-06-24 22:29:05 +04:00
|
|
|
.qdev.props = (Property[]) {
|
|
|
|
DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
|
|
|
|
DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
|
|
|
|
DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
},
|
2009-08-31 16:24:03 +04:00
|
|
|
};
|
|
|
|
|
2010-04-05 22:57:40 +04:00
|
|
|
static SysBusDeviceInfo ohci_sysbus_info = {
|
|
|
|
.init = ohci_init_pxa,
|
|
|
|
.qdev.name = "sysbus-ohci",
|
|
|
|
.qdev.desc = "OHCI USB Controller",
|
|
|
|
.qdev.size = sizeof(OHCISysBusState),
|
|
|
|
.qdev.props = (Property[]) {
|
|
|
|
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
|
|
|
|
DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-08-31 16:24:03 +04:00
|
|
|
static void ohci_register(void)
|
|
|
|
{
|
2010-04-05 22:57:40 +04:00
|
|
|
pci_qdev_register(&ohci_pci_info);
|
|
|
|
sysbus_register_withprop(&ohci_sysbus_info);
|
2009-08-31 16:24:03 +04:00
|
|
|
}
|
|
|
|
device_init(ohci_register);
|