2016-06-01 11:23:44 +03:00
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/*
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* QEMU e1000(e) emulation - shared code
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*
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* Copyright (c) 2008 Qumranet
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-23 15:41:34 +03:00
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* version 2.1 of the License, or (at your option) any later version.
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2016-06-01 11:23:44 +03:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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2018-06-25 15:42:26 +03:00
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#include "qemu/units.h"
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2016-06-01 11:23:44 +03:00
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#include "hw/pci/pci.h"
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#include "net/net.h"
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#include "e1000x_common.h"
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#include "trace.h"
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bool e1000x_rx_ready(PCIDevice *d, uint32_t *mac)
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{
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bool link_up = mac[STATUS] & E1000_STATUS_LU;
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bool rx_enabled = mac[RCTL] & E1000_RCTL_EN;
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bool pci_master = d->config[PCI_COMMAND] & PCI_COMMAND_MASTER;
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if (!link_up || !rx_enabled || !pci_master) {
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trace_e1000x_rx_can_recv_disabled(link_up, rx_enabled, pci_master);
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return false;
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}
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return true;
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}
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bool e1000x_is_vlan_packet(const uint8_t *buf, uint16_t vet)
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{
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2016-06-16 20:17:26 +03:00
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uint16_t eth_proto = lduw_be_p(buf + 12);
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2016-06-01 11:23:44 +03:00
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bool res = (eth_proto == vet);
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trace_e1000x_vlan_is_vlan_pkt(res, eth_proto, vet);
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return res;
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}
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bool e1000x_rx_group_filter(uint32_t *mac, const uint8_t *buf)
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{
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static const int mta_shift[] = { 4, 3, 2, 0 };
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uint32_t f, ra[2], *rp, rctl = mac[RCTL];
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for (rp = mac + RA; rp < mac + RA + 32; rp += 2) {
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if (!(rp[1] & E1000_RAH_AV)) {
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continue;
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}
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ra[0] = cpu_to_le32(rp[0]);
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ra[1] = cpu_to_le32(rp[1]);
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if (!memcmp(buf, (uint8_t *)ra, 6)) {
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trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2,
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MAC_ARG(buf));
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return true;
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}
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}
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trace_e1000x_rx_flt_ucast_mismatch(MAC_ARG(buf));
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f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
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f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
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if (mac[MTA + (f >> 5)] & (1 << (f & 0x1f))) {
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e1000x_inc_reg_if_not_full(mac, MPRC);
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return true;
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}
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trace_e1000x_rx_flt_inexact_mismatch(MAC_ARG(buf),
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(rctl >> E1000_RCTL_MO_SHIFT) & 3,
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f >> 5,
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mac[MTA + (f >> 5)]);
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return false;
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}
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bool e1000x_hw_rx_enabled(uint32_t *mac)
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{
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if (!(mac[STATUS] & E1000_STATUS_LU)) {
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trace_e1000x_rx_link_down(mac[STATUS]);
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return false;
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}
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if (!(mac[RCTL] & E1000_RCTL_EN)) {
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trace_e1000x_rx_disabled(mac[RCTL]);
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return false;
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}
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return true;
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}
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bool e1000x_is_oversized(uint32_t *mac, size_t size)
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{
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/* this is the size past which hardware will
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drop packets when setting LPE=0 */
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static const int maximum_ethernet_vlan_size = 1522;
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/* this is the size past which hardware will
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drop packets when setting LPE=1 */
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2018-06-25 15:42:26 +03:00
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static const int maximum_ethernet_lpe_size = 16 * KiB;
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2016-06-01 11:23:44 +03:00
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if ((size > maximum_ethernet_lpe_size ||
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(size > maximum_ethernet_vlan_size
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&& !(mac[RCTL] & E1000_RCTL_LPE)))
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&& !(mac[RCTL] & E1000_RCTL_SBP)) {
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e1000x_inc_reg_if_not_full(mac, ROC);
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trace_e1000x_rx_oversized(size);
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return true;
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}
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return false;
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}
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void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer)
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{
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e1000x_update_regs_on_link_down(mac, phy);
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trace_e1000x_link_negotiation_start();
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timer_mod(timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
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}
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void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs,
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uint8_t *mac_addr)
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{
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int i;
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mac_regs[RA] = 0;
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mac_regs[RA + 1] = E1000_RAH_AV;
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for (i = 0; i < 4; i++) {
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mac_regs[RA] |= mac_addr[i] << (8 * i);
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mac_regs[RA + 1] |=
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(i < 2) ? mac_addr[i + 4] << (8 * i) : 0;
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}
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qemu_format_nic_info_str(qemu_get_queue(nic), mac_addr);
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trace_e1000x_mac_indicate(MAC_ARG(mac_addr));
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}
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void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy)
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{
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e1000x_update_regs_on_link_up(mac, phy);
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phy[PHY_LP_ABILITY] |= MII_LPAR_LPACK;
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phy[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
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trace_e1000x_link_negotiation_done();
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}
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void
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e1000x_core_prepare_eeprom(uint16_t *eeprom,
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const uint16_t *templ,
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uint32_t templ_size,
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uint16_t dev_id,
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const uint8_t *macaddr)
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{
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uint16_t checksum = 0;
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int i;
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memmove(eeprom, templ, templ_size);
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for (i = 0; i < 3; i++) {
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eeprom[i] = (macaddr[2 * i + 1] << 8) | macaddr[2 * i];
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}
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eeprom[11] = eeprom[13] = dev_id;
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for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
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checksum += eeprom[i];
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}
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checksum = (uint16_t) EEPROM_SUM - checksum;
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eeprom[EEPROM_CHECKSUM_REG] = checksum;
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}
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uint32_t
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e1000x_rxbufsize(uint32_t rctl)
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{
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rctl &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
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E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
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E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
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switch (rctl) {
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
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return 16384;
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
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return 8192;
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
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return 4096;
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case E1000_RCTL_SZ_1024:
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return 1024;
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case E1000_RCTL_SZ_512:
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return 512;
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case E1000_RCTL_SZ_256:
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return 256;
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}
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return 2048;
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}
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void
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e1000x_update_rx_total_stats(uint32_t *mac,
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size_t data_size,
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size_t data_fcs_size)
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{
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static const int PRCregs[6] = { PRC64, PRC127, PRC255, PRC511,
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PRC1023, PRC1522 };
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e1000x_increase_size_stats(mac, PRCregs, data_fcs_size);
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e1000x_inc_reg_if_not_full(mac, TPR);
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mac[GPRC] = mac[TPR];
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/* TOR - Total Octets Received:
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* This register includes bytes received in a packet from the <Destination
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* Address> field through the <CRC> field, inclusively.
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* Always include FCS length (4) in size.
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*/
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e1000x_grow_8reg_if_not_full(mac, TORL, data_size + 4);
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mac[GORCL] = mac[TORL];
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mac[GORCH] = mac[TORH];
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}
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void
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e1000x_increase_size_stats(uint32_t *mac, const int *size_regs, int size)
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{
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if (size > 1023) {
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e1000x_inc_reg_if_not_full(mac, size_regs[5]);
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} else if (size > 511) {
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e1000x_inc_reg_if_not_full(mac, size_regs[4]);
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} else if (size > 255) {
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e1000x_inc_reg_if_not_full(mac, size_regs[3]);
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} else if (size > 127) {
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e1000x_inc_reg_if_not_full(mac, size_regs[2]);
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} else if (size > 64) {
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e1000x_inc_reg_if_not_full(mac, size_regs[1]);
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} else if (size == 64) {
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e1000x_inc_reg_if_not_full(mac, size_regs[0]);
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}
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}
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void
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e1000x_read_tx_ctx_descr(struct e1000_context_desc *d,
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e1000x_txd_props *props)
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{
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uint32_t op = le32_to_cpu(d->cmd_and_length);
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props->ipcss = d->lower_setup.ip_fields.ipcss;
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props->ipcso = d->lower_setup.ip_fields.ipcso;
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props->ipcse = le16_to_cpu(d->lower_setup.ip_fields.ipcse);
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props->tucss = d->upper_setup.tcp_fields.tucss;
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props->tucso = d->upper_setup.tcp_fields.tucso;
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props->tucse = le16_to_cpu(d->upper_setup.tcp_fields.tucse);
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props->paylen = op & 0xfffff;
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props->hdr_len = d->tcp_seg_setup.fields.hdr_len;
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props->mss = le16_to_cpu(d->tcp_seg_setup.fields.mss);
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props->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
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props->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
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props->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
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}
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