2006-05-13 20:11:23 +04:00
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/*
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2006-05-13 20:11:23 +04:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2006-09-24 21:01:44 +04:00
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2009-01-09 23:53:30 +03:00
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/* XXX This file and most of its contents are somewhat misnamed. The
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2006-09-24 21:01:44 +04:00
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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2009-07-21 12:36:37 +04:00
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#include "sysbus.h"
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2007-11-17 20:14:51 +03:00
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#include "pci.h"
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2009-10-30 15:21:06 +03:00
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#include "pci_host.h"
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2010-02-22 13:38:25 +03:00
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#include "rwhandler.h"
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2009-11-11 15:59:56 +03:00
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#include "apb_pci.h"
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2009-01-09 23:53:30 +03:00
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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2009-05-13 21:53:17 +04:00
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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2009-01-09 23:53:30 +03:00
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#else
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2009-05-13 21:53:17 +04:00
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#define APB_DPRINTF(fmt, ...)
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2009-01-09 23:53:30 +03:00
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#endif
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2009-10-13 22:56:27 +04:00
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*
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* APB: "Advanced PCI Bridge (APB) User's Manual",
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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2010-01-30 22:48:12 +03:00
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#define PBM_PCI_IMR_MASK 0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR (1 << 31)
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#define SOFT_POR (1 << 30)
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#define SOFT_XIR (1 << 29)
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#define BTN_POR (1 << 28)
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#define BTN_XIR (1 << 27)
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#define RESET_MASK 0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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2009-07-21 12:36:37 +04:00
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typedef struct APBState {
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SysBusDevice busdev;
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PCIHostState host_state;
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2010-02-22 13:38:25 +03:00
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ReadWriteHandler pci_config_handler;
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2010-01-30 22:48:12 +03:00
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uint32_t iommu[4];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq pci_irqs[32];
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uint32_t reset_control;
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2010-05-12 23:27:23 +04:00
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unsigned int nr_resets;
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2009-07-21 12:36:37 +04:00
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} APBState;
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2006-05-13 20:11:23 +04:00
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2009-10-02 01:12:16 +04:00
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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2007-10-06 15:28:21 +04:00
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uint32_t val)
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2006-05-13 20:11:23 +04:00
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{
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2010-01-30 22:48:12 +03:00
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APBState *s = opaque;
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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s->iommu[(addr & 0xf) >> 2] = val;
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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s->pci_control[(addr & 0x3f) >> 2] = val;
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val &= RESET_MASK;
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control |= val & RESET_WMASK;
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if (val & SOFT_POR) {
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2010-05-12 23:27:23 +04:00
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s->nr_resets = 0;
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2010-01-30 22:48:12 +03:00
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qemu_system_reset_request();
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} else if (val & SOFT_XIR) {
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qemu_system_reset_request();
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}
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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2006-05-13 20:11:23 +04:00
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default:
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2007-10-06 15:28:21 +04:00
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break;
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2006-05-13 20:11:23 +04:00
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}
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}
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static uint32_t apb_config_readl (void *opaque,
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2009-10-02 01:12:16 +04:00
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target_phys_addr_t addr)
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2006-05-13 20:11:23 +04:00
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{
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2010-01-30 22:48:12 +03:00
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APBState *s = opaque;
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2006-05-13 20:11:23 +04:00
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uint32_t val;
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2010-01-30 22:48:12 +03:00
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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val = 0;
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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val = s->iommu[(addr & 0xf) >> 2];
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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val = 0;
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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val = s->pci_irq_map[(addr & 0x3f) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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val = s->pci_control[(addr & 0x3f) >> 2];
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val = s->reset_control;
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} else {
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val = 0;
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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2006-05-13 20:11:23 +04:00
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default:
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2007-10-06 15:28:21 +04:00
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val = 0;
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break;
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2006-05-13 20:11:23 +04:00
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}
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2010-01-30 22:48:12 +03:00
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
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2006-05-13 20:11:23 +04:00
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return val;
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}
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2009-08-25 22:29:31 +04:00
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static CPUWriteMemoryFunc * const apb_config_write[] = {
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2006-05-13 20:11:23 +04:00
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&apb_config_writel,
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&apb_config_writel,
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&apb_config_writel,
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};
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2009-08-25 22:29:31 +04:00
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static CPUReadMemoryFunc * const apb_config_read[] = {
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2006-05-13 20:11:23 +04:00
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&apb_config_readl,
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&apb_config_readl,
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&apb_config_readl,
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};
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2010-02-22 13:38:25 +03:00
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static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
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2010-01-12 00:20:53 +03:00
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uint32_t val, int size)
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{
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2010-02-22 13:38:25 +03:00
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APBState *s = container_of(h, APBState, pci_config_handler);
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val = qemu_bswap_len(val, size);
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2010-01-12 00:20:53 +03:00
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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2010-02-22 12:40:19 +03:00
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pci_data_write(s->host_state.bus, addr, val, size);
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2010-01-12 00:20:53 +03:00
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}
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2010-02-22 13:38:25 +03:00
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static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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2010-01-12 00:20:53 +03:00
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int size)
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{
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uint32_t ret;
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2010-02-22 13:38:25 +03:00
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APBState *s = container_of(h, APBState, pci_config_handler);
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2010-01-12 00:20:53 +03:00
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2010-02-22 12:40:19 +03:00
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ret = pci_data_read(s->host_state.bus, addr, size);
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2010-02-22 13:38:25 +03:00
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ret = qemu_bswap_len(ret, size);
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2010-01-12 00:20:53 +03:00
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
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return ret;
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}
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2009-10-02 01:12:16 +04:00
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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2006-05-13 20:11:23 +04:00
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uint32_t val)
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{
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2009-09-20 20:05:47 +04:00
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cpu_outb(addr & IOPORTS_MASK, val);
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2006-05-13 20:11:23 +04:00
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}
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2009-10-02 01:12:16 +04:00
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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2006-05-13 20:11:23 +04:00
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uint32_t val)
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{
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2010-01-29 21:15:21 +03:00
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cpu_outw(addr & IOPORTS_MASK, bswap16(val));
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2006-05-13 20:11:23 +04:00
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}
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2009-10-02 01:12:16 +04:00
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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2006-05-13 20:11:23 +04:00
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uint32_t val)
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{
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2010-01-29 21:15:21 +03:00
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cpu_outl(addr & IOPORTS_MASK, bswap32(val));
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2006-05-13 20:11:23 +04:00
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}
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2009-10-02 01:12:16 +04:00
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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2006-05-13 20:11:23 +04:00
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{
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uint32_t val;
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2009-09-20 20:05:47 +04:00
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val = cpu_inb(addr & IOPORTS_MASK);
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2006-05-13 20:11:23 +04:00
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return val;
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}
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2009-10-02 01:12:16 +04:00
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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2006-05-13 20:11:23 +04:00
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{
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uint32_t val;
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2010-01-29 21:15:21 +03:00
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val = bswap16(cpu_inw(addr & IOPORTS_MASK));
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2006-05-13 20:11:23 +04:00
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return val;
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}
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2009-10-02 01:12:16 +04:00
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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2006-05-13 20:11:23 +04:00
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{
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uint32_t val;
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2010-01-29 21:15:21 +03:00
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val = bswap32(cpu_inl(addr & IOPORTS_MASK));
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2006-05-13 20:11:23 +04:00
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return val;
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}
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2009-08-25 22:29:31 +04:00
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static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
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2006-05-13 20:11:23 +04:00
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&pci_apb_iowriteb,
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&pci_apb_iowritew,
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&pci_apb_iowritel,
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};
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2009-08-25 22:29:31 +04:00
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static CPUReadMemoryFunc * const pci_apb_ioread[] = {
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2006-05-13 20:11:23 +04:00
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&pci_apb_ioreadb,
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&pci_apb_ioreadw,
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&pci_apb_ioreadl,
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};
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2006-09-24 21:01:44 +04:00
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/* The APB host has an IRQ line for each IRQ line of each slot. */
|
2006-09-24 04:16:34 +04:00
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
|
2006-05-13 20:11:23 +04:00
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{
|
2006-09-24 21:01:44 +04:00
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return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
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}
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int bus_offset;
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if (pci_dev->devfn & 1)
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bus_offset = 16;
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else
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bus_offset = 0;
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return bus_offset + irq_num;
|
2006-09-24 04:16:34 +04:00
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}
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2009-08-28 17:28:17 +04:00
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
|
2006-09-24 04:16:34 +04:00
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{
|
2010-01-30 22:48:12 +03:00
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|
APBState *s = opaque;
|
2009-08-28 17:28:17 +04:00
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2006-09-24 21:01:44 +04:00
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/* PCI IRQ map onto the first 32 INO. */
|
2010-01-30 22:48:12 +03:00
|
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|
if (irq_num < 32) {
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|
|
if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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|
|
APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->pci_irqs[irq_num], level);
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|
} else {
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|
|
APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
|
|
|
|
qemu_irq_lower(s->pci_irqs[irq_num]);
|
|
|
|
}
|
|
|
|
}
|
2006-05-13 20:11:23 +04:00
|
|
|
}
|
|
|
|
|
2009-11-11 15:33:54 +03:00
|
|
|
static void apb_pci_bridge_init(PCIBus *b)
|
|
|
|
{
|
|
|
|
PCIDevice *dev = pci_bridge_get_device(b);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* command register:
|
|
|
|
* According to PCI bridge spec, after reset
|
|
|
|
* bus master bit is off
|
|
|
|
* memory space enable bit is off
|
|
|
|
* According to manual (805-1251.pdf).
|
|
|
|
* the reset value should be zero unless the boot pin is tied high
|
|
|
|
* (which is true) and thus it should be PCI_COMMAND_MEMORY.
|
|
|
|
*/
|
|
|
|
pci_set_word(dev->config + PCI_COMMAND,
|
2010-02-14 11:27:19 +03:00
|
|
|
PCI_COMMAND_MEMORY);
|
|
|
|
pci_set_word(dev->config + PCI_STATUS,
|
|
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
|
|
pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
|
|
|
|
pci_set_byte(dev->config + PCI_HEADER_TYPE,
|
|
|
|
pci_get_byte(dev->config + PCI_HEADER_TYPE) |
|
|
|
|
PCI_HEADER_TYPE_MULTI_FUNCTION);
|
2009-11-11 15:33:54 +03:00
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
PCIBus *pci_apb_init(target_phys_addr_t special_base,
|
|
|
|
target_phys_addr_t mem_base,
|
2009-01-10 14:33:32 +03:00
|
|
|
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
2009-07-21 12:36:37 +04:00
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
|
|
|
APBState *d;
|
2010-01-30 22:48:12 +03:00
|
|
|
unsigned int i;
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2006-09-24 21:01:44 +04:00
|
|
|
/* Ultrasparc PBM main bus */
|
2009-07-21 12:36:37 +04:00
|
|
|
dev = qdev_create(NULL, "pbm");
|
2009-10-07 03:15:58 +04:00
|
|
|
qdev_init_nofail(dev);
|
2009-07-21 12:36:37 +04:00
|
|
|
s = sysbus_from_qdev(dev);
|
|
|
|
/* apb_config */
|
2010-01-10 21:25:48 +03:00
|
|
|
sysbus_mmio_map(s, 0, special_base);
|
2009-07-21 12:36:37 +04:00
|
|
|
/* pci_ioport */
|
|
|
|
sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
|
2010-01-22 21:39:49 +03:00
|
|
|
/* pci_config */
|
2009-07-21 12:36:37 +04:00
|
|
|
sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
|
|
|
|
/* mem_data */
|
2010-01-22 21:39:49 +03:00
|
|
|
sysbus_mmio_map(s, 3, mem_base);
|
2009-07-21 12:36:37 +04:00
|
|
|
d = FROM_SYSBUS(APBState, s);
|
2009-09-13 12:32:40 +04:00
|
|
|
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
|
2010-01-30 22:48:12 +03:00
|
|
|
pci_apb_set_irq, pci_pbm_map_irq, d,
|
2009-07-21 12:36:37 +04:00
|
|
|
0, 32);
|
2009-12-27 23:52:39 +03:00
|
|
|
pci_bus_set_mem_base(d->host_state.bus, mem_base);
|
|
|
|
|
2010-01-30 22:48:12 +03:00
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
sysbus_connect_irq(s, i, pic[i]);
|
|
|
|
}
|
|
|
|
|
2009-07-21 12:36:37 +04:00
|
|
|
pci_create_simple(d->host_state.bus, 0, "pbm");
|
|
|
|
/* APB secondary busses */
|
2009-10-30 15:20:57 +03:00
|
|
|
*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
|
|
|
|
PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
|
|
|
|
pci_apb_map_irq,
|
2009-07-21 12:36:37 +04:00
|
|
|
"Advanced PCI Bus secondary bridge 1");
|
2009-11-11 15:33:54 +03:00
|
|
|
apb_pci_bridge_init(*bus2);
|
|
|
|
|
2009-10-30 15:20:57 +03:00
|
|
|
*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
|
|
|
|
PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
|
|
|
|
pci_apb_map_irq,
|
2009-07-21 12:36:37 +04:00
|
|
|
"Advanced PCI Bus secondary bridge 2");
|
2009-11-11 15:33:54 +03:00
|
|
|
apb_pci_bridge_init(*bus3);
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2009-07-21 12:36:37 +04:00
|
|
|
return d->host_state.bus;
|
|
|
|
}
|
|
|
|
|
2010-01-30 22:48:12 +03:00
|
|
|
static void pci_pbm_reset(DeviceState *d)
|
2009-07-21 12:36:37 +04:00
|
|
|
{
|
2010-01-30 22:48:12 +03:00
|
|
|
unsigned int i;
|
|
|
|
APBState *s = container_of(d, APBState, busdev.qdev);
|
2009-07-21 12:36:37 +04:00
|
|
|
|
2010-01-30 22:48:12 +03:00
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
|
|
|
|
}
|
|
|
|
|
2010-05-12 23:27:23 +04:00
|
|
|
if (s->nr_resets++ == 0) {
|
2010-01-30 22:48:12 +03:00
|
|
|
/* Power on reset */
|
|
|
|
s->reset_control = POR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_pbm_init_device(SysBusDevice *dev)
|
|
|
|
{
|
2009-07-21 12:36:37 +04:00
|
|
|
APBState *s;
|
2010-01-22 21:39:49 +03:00
|
|
|
int pci_mem_data, apb_config, pci_ioport, pci_config;
|
2010-01-30 22:48:12 +03:00
|
|
|
unsigned int i;
|
2009-07-21 12:36:37 +04:00
|
|
|
|
|
|
|
s = FROM_SYSBUS(APBState, dev);
|
2010-01-30 22:48:12 +03:00
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
|
|
|
|
}
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
sysbus_init_irq(dev, &s->pci_irqs[i]);
|
|
|
|
}
|
|
|
|
|
2009-07-21 12:36:37 +04:00
|
|
|
/* apb_config */
|
2009-06-14 12:38:51 +04:00
|
|
|
apb_config = cpu_register_io_memory(apb_config_read,
|
2007-10-06 15:28:21 +04:00
|
|
|
apb_config_write, s);
|
2010-01-10 21:25:48 +03:00
|
|
|
sysbus_init_mmio(dev, 0x10000ULL, apb_config);
|
2009-07-21 12:36:37 +04:00
|
|
|
/* pci_ioport */
|
2009-06-14 12:38:51 +04:00
|
|
|
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
|
2006-05-13 20:11:23 +04:00
|
|
|
pci_apb_iowrite, s);
|
2009-07-21 12:36:37 +04:00
|
|
|
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
|
2010-01-12 00:20:53 +03:00
|
|
|
/* pci_config */
|
2010-02-22 13:38:25 +03:00
|
|
|
s->pci_config_handler.read = apb_pci_config_read;
|
|
|
|
s->pci_config_handler.write = apb_pci_config_write;
|
|
|
|
pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
|
|
|
|
assert(pci_config >= 0);
|
2010-01-12 00:20:53 +03:00
|
|
|
sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
|
2009-07-21 12:36:37 +04:00
|
|
|
/* mem_data */
|
2010-03-21 23:37:50 +03:00
|
|
|
pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
|
2009-07-21 12:36:37 +04:00
|
|
|
sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
|
2009-08-14 12:36:05 +04:00
|
|
|
return 0;
|
2009-07-21 12:36:37 +04:00
|
|
|
}
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2009-08-14 12:36:05 +04:00
|
|
|
static int pbm_pci_host_init(PCIDevice *d)
|
2009-07-21 12:36:37 +04:00
|
|
|
{
|
2009-01-26 18:37:35 +03:00
|
|
|
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
|
|
|
|
pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
|
2010-02-14 11:27:19 +03:00
|
|
|
pci_set_word(d->config + PCI_COMMAND,
|
|
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
pci_set_word(d->config + PCI_STATUS,
|
|
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
2009-02-01 22:26:20 +03:00
|
|
|
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
|
2010-02-14 11:27:19 +03:00
|
|
|
pci_set_byte(d->config + PCI_HEADER_TYPE,
|
|
|
|
PCI_HEADER_TYPE_NORMAL);
|
2009-08-14 12:36:05 +04:00
|
|
|
return 0;
|
2009-07-21 12:36:37 +04:00
|
|
|
}
|
2006-09-24 21:01:44 +04:00
|
|
|
|
2009-07-21 12:36:37 +04:00
|
|
|
static PCIDeviceInfo pbm_pci_host_info = {
|
|
|
|
.qdev.name = "pbm",
|
|
|
|
.qdev.size = sizeof(PCIDevice),
|
|
|
|
.init = pbm_pci_host_init,
|
2010-01-27 00:59:57 +03:00
|
|
|
.header_type = PCI_HEADER_TYPE_BRIDGE,
|
2009-07-21 12:36:37 +04:00
|
|
|
};
|
|
|
|
|
2010-01-30 22:48:12 +03:00
|
|
|
static SysBusDeviceInfo pbm_host_info = {
|
|
|
|
.qdev.name = "pbm",
|
|
|
|
.qdev.size = sizeof(APBState),
|
|
|
|
.qdev.reset = pci_pbm_reset,
|
|
|
|
.init = pci_pbm_init_device,
|
|
|
|
};
|
2009-07-21 12:36:37 +04:00
|
|
|
static void pbm_register_devices(void)
|
|
|
|
{
|
2010-01-30 22:48:12 +03:00
|
|
|
sysbus_register_withprop(&pbm_host_info);
|
2009-07-21 12:36:37 +04:00
|
|
|
pci_qdev_register(&pbm_pci_host_info);
|
2006-05-13 20:11:23 +04:00
|
|
|
}
|
2009-07-21 12:36:37 +04:00
|
|
|
|
|
|
|
device_init(pbm_register_devices)
|