2021-01-08 22:09:42 +03:00
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/*
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* Nuvoton NPCM7xx ADC Module
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_ADC_H
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#define NPCM7XX_ADC_H
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#include "hw/clock.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#define NPCM7XX_ADC_NUM_INPUTS 8
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/**
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* This value should not be changed unless write_adc_calibration function in
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* hw/arm/npcm7xx.c is also changed.
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*/
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#define NPCM7XX_ADC_NUM_CALIB 2
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/**
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* struct NPCM7xxADCState - Analog to Digital Converter Module device state.
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* @parent: System bus device.
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* @iomem: Memory region through which registers are accessed.
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* @conv_timer: The timer counts down remaining cycles for the conversion.
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* @irq: GIC interrupt line to fire on expiration (if enabled).
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* @con: The Control Register.
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* @data: The Data Buffer.
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* @clock: The ADC Clock.
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* @adci: The input voltage in units of uV. 1uv = 1e-6V.
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* @vref: The external reference voltage.
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* @iref: The internal reference voltage, initialized at launch time.
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* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
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*/
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2023-01-09 17:03:02 +03:00
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struct NPCM7xxADCState {
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2021-01-08 22:09:42 +03:00
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SysBusDevice parent;
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MemoryRegion iomem;
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QEMUTimer conv_timer;
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qemu_irq irq;
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uint32_t con;
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uint32_t data;
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Clock *clock;
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/* Voltages are in unit of uV. 1V = 1000000uV. */
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uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
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uint32_t vref;
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uint32_t iref;
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uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
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2023-01-09 17:03:02 +03:00
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};
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2021-01-08 22:09:42 +03:00
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#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
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2023-01-09 17:03:02 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
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2021-01-08 22:09:42 +03:00
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#endif /* NPCM7XX_ADC_H */
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